DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 14 July 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jing et al. (“Construction and optimization of heterogeneous memory system based on NUMA architecture”).
In regards to claims 1, 8, and 15, Jing teaches a computing system comprising:
a memory (DRAM and NVM, figure 5) configured to store address mappings (“the page table entry”, section III(A));
a client comprising circuitry configured to generate address translation requests (“The steps of data request and data cache in hierarchical heterogeneous memory architecture are shown in Figure 3:”, section III(A), “virtual address”, figure 3); and
one or more translation lookaside buffers (TLBs) dedicated for storage of address translations (“TLB entry”, section III(A)), each comprising:
a plurality of entries (“TLB entry”, section III(A)), each configured to store an address mapping retrieved from the memory (“DRAM or NVM physical page number”, figure 2(a)) and metadata that indicates a type of the address mapping (“the tag a S identity TLB physical page fields in table item memory storage type, S to 0, TLB list items in the physical page number in the corresponding page in the NVM, S to 1, the page corresponding to the physical page number in the TLB entry is stored in the DRAM cache”, section III(A)); and
circuitry (“memory architecture”, section III(A));
wherein circuitry of a first TLB of the one or more TLBs is configured to:
receive, from the client, an address translation request generated based on a memory access request and comprising an initial address of the memory access request (“The steps of data request and data cache in hierarchical heterogeneous memory architecture are shown in Figure 3:”, section III(A), “virtual address”, figure 3);
retrieve, from a first entry of the plurality of entries, a final address corresponding to the initial address (“TLB obtains the physical address”, figure 3), wherein each entry of the plurality of entries stores:
an address mapping (“DRAM or NVM physical page number”, figure 2(a)); and
metadata that indicates a type of the address mapping (“the tag a S identity TLB physical page fields in table item memory storage type, S to 0, TLB list items in the physical page number in the corresponding page in the NVM, S to 1, the page corresponding to the physical page number in the TLB entry is stored in the DRAM cache”, section III(A));
wherein the metadata stored in the plurality of entries distinguishes among a plurality of different types of address space translations, including two or more types that each provide a physical address pointing to a physical memory location of target data for a memory access request (“the tag a S identity TLB physical page fields in table item memory storage type, S to 0, TLB list items in the physical page number in the corresponding page in the NVM, S to 1, the page corresponding to the physical page number in the TLB entry is stored in the DRAM cache”, section III(A)); and
send the final address to the client for use in accessing target data of the memory access request (“Access DRAM cache”, figure 3; “Access to NVM main memory”, figure 3).
In regards to claims 2, 9, and 16, Jing further teaches that the plurality of different types of address space translations comprises:
a first type of address space translation in which an initial address is translated to a physical address pointing to a physical memory location in a local memory of the client (“S to 1, the page corresponding to the physical page number in the TLB entry is stored in the DRAM cache”, section III(A)); and
a second type of address space translation in which an initial address is translated to a physical address pointing to a physical memory location in a system memory (“S to 0, TLB list items in the physical page number in the corresponding page in the NVM”, section III(A)).
In regards to claims 3, 10, and 17, Jing further teaches the metadata of an entry further comprises an indication of one or more of: a source of a corresponding address translation request (AID bits, figure 2(b), a virtual function identifier, and a data access permission that corresponds to the address mapping (D and G bits, figure 2(b)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jing et al. (“Construction and optimization of heterogeneous memory system based on NUMA architecture”) in view of Li et al. (US 2013/0117521).
In regards to claims 4, 11, and 18, Jing teaches claims 1, 8, and 15. Jing fails to teach that the metadata of an entry further comprises an indication of a destination identifier that identifies a memory device. Li teaches that the metadata of an entry further comprises an indication of a destination identifier that identifies a memory device (“Either after the TLB is refilled as in block 121, or if a TLB hit happens during the physical address to virtual address translation as in block 109, the requestor compares the BCID and CFW registers of the requesting tile with the BCID and CFW stored in the current TLB entry (129 in FIG. 1B). If the two match, base core ID and configuration word fields in requestor tile are used to compute dynamic home node (131). At the dynamic home node, the directory will be looked up (133). If no tile has the item (135), the item is copied from the main memory into a cache of the requestor tile (137), and directory records the tile as the current owner of the item (139). If the directory indicates another tile(s) has the item, the item is fetched from the owner to the requestor core (141).”, paragraph 0015) which “makes it possible to service most on-chip traffic within a virtual domain, minimizing message travel to more distant locations” (paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Jing with Li such that the metadata of an entry further comprises an indication of a destination identifier that identifier a memory device which “makes it possible to service most on-chip traffic within a virtual domain, minimizing message travel to more distant locations” (id.).
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jing et al. (“Construction and optimization of heterogeneous memory system based on NUMA architecture”) in view of Smith et al. (US 2018/0307622).
In regards to claims 5 and 12, Jing further teaches receiving, from the client by the circuitry of the first TLB, a second address translation request (“The steps of data request and data cache in hierarchical heterogeneous memory architecture are shown in Figure 3:”, section III(A); “virtual address”, figure 3) comprising a second address and a second type of address mapping (S = 1 ? leads to No, figure 3); and
retrieving, from a second entry of the plurality of entries by circuitry of the TLB that corresponds to the second address and the second type of address mapping, an address mapping that corresponds to the second address (“TLB obtains the physical address, whether the DRAM cache is hit, and the access frequency”, figure 3).
Jing fails to teach that the address mapping corresponds to a virtual function. Smith teaches that the address mapping corresponds to a virtual function (“In one embodiment, GPU 130 is configured to perform a lookup of the TLBs for a first translation request using a first virtual address, first virtual memory identifier (VMID), and first virtual function identifier (VFID).”, paragraph 0019; “first translation lookaside buffer (TLB), wherein the first TLB comprises a cache of entries storing virtual-to-physical address translations”, claim 1; “In one embodiment, the index 310B portion of virtual address, VMID 315, and VFID 320 are utilized as the cache index 325 to locate a given index of cache 330.”, paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Jing with Smith such that the address mapping corresponds to a virtual function in order to efficiently virtualize PCIe devices.
Claims 6, 7, 13, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jing et al. (“Construction and optimization of heterogeneous memory system based on NUMA architecture”) in view of Chen et al. (US 2014/0006681).
In regards to claims 6, 13, and 19, Jing further teaches an address mapping being unavailable in the plurality of entries of the TLB (TLB obtains the physical address to No arrow, figure 3); and
store, in a selected entry of the first TLB, an address mapping (Update TLB, figure 3) and metadata that indicates that the address mapping is of the first type (“the tag a S identity TLB physical page fields in table item memory storage type, S to 0, TLB list items in the physical page number in the corresponding page in the NVM, S to 1, the page corresponding to the physical page number in the TLB entry is stored in the DRAM cache”, section III(A)).
Jing fails to teach responsive to an address mapping being unavailable in the plurality of entries of the first TLB, the circuitry of the first TLB is configured to:
retrieve an address mapping from a given entry of a second TLB of the one or more TLBs, wherein each entry of the second TLB stores an address mapping of a first type; and
store, in a selected entry of the first TLB, the address mapping from the given entry of the second TLB.
Chen teaches responsive to an address mapping being unavailable in the plurality of entries of the first TLB (“Assume that uTLB 226 either does not contain an address mapping for the guest virtual address 102, or does contain an address mapping which is no longer valid.”, paragraph 0051), the circuitry of the first TLB is configured to:
retrieve an address mapping from a given entry of a second TLB of the one or more TLBs (“In particular, as shown in FIG. 5C, a lookup is performed against the guest TLB 304 to perform a translation of the guest virtual address 102 to obtain the guest physical address.”, paragraph 0051), wherein each entry of the second TLB stores an address mapping of a first type (“the MMU 224 includes a guest TLB 304 to provide a translation of an address input 320 in the form of a guest virtual address to a guest physical address”, paragraph 0037); and
store, in a selected entry of the first TLB, the address mapping from the given entry of the second TLB (“FIG. 5E illustrates the action of storing these address translations from the L2 cache (guest TLB 304 and root TLB 306) to an entry 502 within the L1 cache (uTLB 226).”, paragraph 0052)
which “allows future translations for the same guest virtual address 102 to occur with a single lookup of the uTLB 226.” (paragraph 0052)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Jing with Chen such that responsive to an address mapping being unavailable in the plurality of entries of the first TLB, the circuitry of the first TLB is configured to:
retrieve an address mapping from a given entry of a second TLB of the one or more TLBs, wherein each entry of the second TLB stores an address mapping of a first type; and
store, in a selected entry of the first TLB, the address mapping from the given entry of the second TLB
which “allows future translations for the same guest virtual address 102 to occur with a single lookup of the uTLB 226.” (id.)
In regards to claims 7, 14, and 20, Chen further teaches that the first type of address mapping corresponds to a guest virtual address to a physical address in a system memory (“the MMU 224 includes a guest TLB 304 to provide a translation of an address input 320 in the form of a guest virtual address to a guest physical address”, paragraph 0037).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 9 October 2026
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