DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hunt (US 2012/0215979).
In regards to claims 1 and 8, Hunt teaches an integrated circuit comprising:
a first translation lookaside buffer (TLB) dedicated for storage of address translations, the TLB comprising circuitry (“In one embodiment, for example, the cache 110 may implement a translation lookaside buffer (‘TLB’), a page directory cache (‘PDC’) and a Guest TLB cache.”, paragraph 0015; “For example, if three types of data are stored in the cache, a two-bit encoding system could be used to identify the data type. For example, in one embodiment a TLB entry may be designated with the code ‘01,’ a PDC entry may be designated with the code ‘10,’ and a Guest TLB entry could be designated with the code ‘11.’”, paragraph 0030) configured to:
receive, from a client, a first address translation request comprising a first initial address (“The processor then determines the tag 124, data type 126 and/or identification of the corresponding entry to be located, and the index which specifies which location or locations at which the data may reside in the cache. (Step 220).”, paragraph 0031);
retrieve, from a first entry of a plurality of entries of the first TLB, a first final address corresponding to the first initial address, wherein each entry of the plurality of entries stores (“If an entry is found, the cache 110 may return a hit indication and the associated data. (Step 242). For example, the processor may be looking for a virtual to physical address translation, and thus looking for a TLB entry in the cache 110. Accordingly, if the cache returns a cache hit, indicating that the supplied virtual address and data type (TLB) has been found, the cache 110 returns data stored in a corresponding entry in the data array 130, which in this example would be a physical address.”, paragraph 0032):
an address mapping between a source address space and a destination address space (“The available data types 126 may include, but are not limited to, a TLB entry, a PDC entry and a Guest TLB entry.”, paragraph 0017; “A translation lookaside buffer (‘TLB’) is a form of cache used in most processors to quickly identify a location of data stored in an external memory (i.e., external to the processor 100) by associating a virtual address (used by software to refer to specific data items) with a physical address (corresponding to the actual location where the processor hardware has stored that data item).”, paragraph 0018; “In such a system, a Guest TLB may be used to cache the translations from Guest Virtual addresses to Guest Physical addresses.”, paragraph 0025); and
metadata that indicates a type of the address mapping, such that the plurality of entries collectively distinguishes among two or more different types of address space translations (“The data type 126 in a given tag entry 122 in the tag array indicates the type of data currently stored in the corresponding data entry 132. The available data types 126 may include, but are not limited to, a TLB entry, a PDC entry and a Guest TLB entry.”, paragraphs 0016-0017; “For example, if three types of data are stored in the cache, a two-bit encoding system could be used to identify the data type. For example, in one embodiment a TLB entry may be designated with the code ‘01,’ a PDC entry may be designated with the code ‘10,’ and a Guest TLB entry could be designated with the code ‘11.’”, paragraph 0030); and
send the first final address to the client (“If an entry is found, the cache 110 may return a hit indication and the associated data. (Step 242). For example, the processor may be looking for a virtual to physical address translation, and thus looking for a TLB entry in the cache 110. Accordingly, if the cache returns a cache hit, indicating that the supplied virtual address and data type (TLB) has been found, the cache 110 returns data stored in a corresponding entry in the data array 130, which in this example would be a physical address.”, paragraph 0032).
In regards to claim 15, Hunt teaches a computing system comprising:
a memory configured to store address mappings (“A page table is a data structure used by a virtual memory system in an operating system (‘OS’) to store a mapping between virtual addresses and physical addresses.”, paragraph 0019; “A page walk is a time-intensive process, as it involves reading the contents of multiple memory locations and using them to compute the physical address.”, paragraph 0020);
a client comprising circuitry configured to generate address translation requests (“The processor 100 supplies an address (in the case of a TLB, this is a virtual address) for which it would like the cache no to return the corresponding physical address.”, paragraph 0018); and
one or more translation lookaside buffers (TLBs) dedicated for storage of address translations (“In one embodiment, for example, the cache 110 may implement a translation lookaside buffer (‘TLB’), a page directory cache (‘PDC’) and a Guest TLB cache.”, paragraph 0015; “For example, if three types of data are stored in the cache, a two-bit encoding system could be used to identify the data type. For example, in one embodiment a TLB entry may be designated with the code ‘01,’ a PDC entry may be designated with the code ‘10,’ and a Guest TLB entry could be designated with the code ‘11.’”, paragraph 0030), each comprising:
a plurality of entries, each configured to store an address mapping retrieved from the memory (“If an entry is found, the cache 110 may return a hit indication and the associated data. (Step 242). For example, the processor may be looking for a virtual to physical address translation, and thus looking for a TLB entry in the cache 110. Accordingly, if the cache returns a cache hit, indicating that the supplied virtual address and data type (TLB) has been found, the cache 110 returns data stored in a corresponding entry in the data array 130, which in this example would be a physical address.”, paragraph 0032) and metadata that indicates a type of the address mapping (“The data type 126 in a given tag entry 122 in the tag array indicates the type of data currently stored in the corresponding data entry 132. The available data types 126 may include, but are not limited to, a TLB entry, a PDC entry and a Guest TLB entry.”, paragraphs 0016-0017); and
circuitry (“A translation lookaside buffer (‘TLB’) is a form of cache used in most processors to quickly identify a location of data stored in an external memory (i.e., external to the processor 100) by associating a virtual address (used by software to refer to specific data items) with a physical address (corresponding to the actual location where the processor hardware has stored that data item).”, paragraph 0018);
wherein circuitry of a first TLB of the one or more TLBs is configured to:
receive, from the client, a first address translation request comprising an initial address (“The processor then determines the tag 124, data type 126 and/or identification of the corresponding entry to be located, and the index which specifies which location or locations at which the data may reside in the cache. (Step 220).”, paragraph 0031);
retrieve, from a first entry of the plurality of entries, a final address corresponding to the initial address (“If an entry is found, the cache 110 may return a hit indication and the associated data. (Step 242). For example, the processor may be looking for a virtual to physical address translation, and thus looking for a TLB entry in the cache 110. Accordingly, if the cache returns a cache hit, indicating that the supplied virtual address and data type (TLB) has been found, the cache 110 returns data stored in a corresponding entry in the data array 130, which in this example would be a physical address.”, paragraph 0032), wherein each entry of the plurality of entries stores:
an address mapping between a source address space and a destination address space (“The available data types 126 may include, but are not limited to, a TLB entry, a PDC entry and a Guest TLB entry.”, paragraph 0017; “A translation lookaside buffer (‘TLB’) is a form of cache used in most processors to quickly identify a location of data stored in an external memory (i.e., external to the processor 100) by associating a virtual address (used by software to refer to specific data items) with a physical address (corresponding to the actual location where the processor hardware has stored that data item).”, paragraph 0018; “In such a system, a Guest TLB may be used to cache the translations from Guest Virtual addresses to Guest Physical addresses.”, paragraph 0025); and
metadata that indicates a type of the address mapping, such that the plurality of entries collectively distinguishes among two or more different types of address space translations (“The data type 126 in a given tag entry 122 in the tag array indicates the type of data currently stored in the corresponding data entry 132. The available data types 126 may include, but are not limited to, a TLB entry, a PDC entry and a Guest TLB entry.”, paragraphs 0016-0017; “For example, if three types of data are stored in the cache, a two-bit encoding system could be used to identify the data type. For example, in one embodiment a TLB entry may be designated with the code ‘01,’ a PDC entry may be designated with the code ‘10,’ and a Guest TLB entry could be designated with the code ‘11.’”, paragraph 0030); and
send the first final address to the client (“If an entry is found, the cache 110 may return a hit indication and the associated data. (Step 242). For example, the processor may be looking for a virtual to physical address translation, and thus looking for a TLB entry in the cache 110. Accordingly, if the cache returns a cache hit, indicating that the supplied virtual address and data type (TLB) has been found, the cache 110 returns data stored in a corresponding entry in the data array 130, which in this example would be a physical address.”, paragraph 0032).
In regards to claims 2, 9, and 16, Hunt further teaches that the address mapping corresponds to any of: a virtual address to a physical address in a local memory, a virtual address to a physical address in a system memory, and a guest physical address to a physical address in the system memory (“The available data types 126 may include, but are not limited to, a TLB entry, a PDC entry and a Guest TLB entry.”, paragraph 0017; “A translation lookaside buffer (‘TLB’) is a form of cache used in most processors to quickly identify a location of data stored in an external memory (i.e., external to the processor 100) by associating a virtual address (used by software to refer to specific data items) with a physical address (corresponding to the actual location where the processor hardware has stored that data item).”, paragraph 0018; “In such a system, a Guest TLB may be used to cache the translations from Guest Virtual addresses to Guest Physical addresses.”, paragraph 0025).
In regards to claims 3, 10, and 17, Hunt further teaches that the metadata of an entry further comprises an indication of one or more of: a source of a corresponding address translation request (“hardware address space identifier (‘ASID’) bits (which indicate which process or OS a given entry is associated with)”, paragraph 0037), a virtual function identifier, and a data access permission that corresponds to the address mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hunt (US 2012/0215979) in view of Li et al. (US 2013/0117521).
In regards to claims 4, 11, and 18, Hunt teaches claims 1, 8, and 15. Hunt fails to teach that the metadata of an entry further comprises an indication of a destination identifier that identifier a memory device. Li teaches that the metadata of an entry further comprises an indication of a destination identifier that identifies a memory device (“Either after the TLB is refilled as in block 121, or if a TLB hit happens during the physical address to virtual address translation as in block 109, the requestor compares the BCID and CFW registers of the requesting tile with the BCID and CFW stored in the current TLB entry (129 in FIG. 1B). If the two match, base core ID and configuration word fields in requestor tile are used to compute dynamic home node (131). At the dynamic home node, the directory will be looked up (133). If no tile has the item (135), the item is copied from the main memory into a cache of the requestor tile (137), and directory records the tile as the current owner of the item (139). If the directory indicates another tile(s) has the item, the item is fetched from the owner to the requestor core (141).”, paragraph 0015) which “makes it possible to service most on-chip traffic within a virtual domain, minimizing message travel to more distant locations” (paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hunt with Li such that the metadata of an entry further comprises an indication of a destination identifier that identifier a memory device which “makes it possible to service most on-chip traffic within a virtual domain, minimizing message travel to more distant locations” (id.).
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hunt (US 2012/0215979) in view of Smith et al. (US 2018/0307622).
In regards to claims 5 and 12, Hunt further teaches receiving, from the client by the circuitry of the first TLB, a second address translation request comprising a second address and a second type of address mapping (“A Page Directory Cache (‘PDC’) is used to store some of the steps required during a page walk to determine a virtual address to physical address mapping. Thus, when no TLB entry exists to provide the complete mapping from virtual to physical mapping, the time taken to perform the memory reads (or steps) along the page walk may be reduced if some of these steps are stored in a cache (called a Page Directory Cache). A PDC entry has a tag 124 formed from a sub-set of the virtual address and a data type 126 which indicates that the entry is a PDC entry and what level or levels of the page walk the entry represents. The data array entry 132 for a given PDC entry is the physical address of the next step of the page walk which must be performed to complete the translation of the supplied virtual address to the final physical address which is sought.”, paragraph 0022); and
retrieving, from a second entry of the plurality of entries by circuitry of the TLB that corresponds to the second address and the second type of address mapping, an address mapping that corresponds to the second address (id.).
Hunt fails to teach that the address mapping corresponds to a virtual function. Smith teaches that the address mapping corresponds to a virtual function (“In one embodiment, GPU 130 is configured to perform a lookup of the TLBs for a first translation request using a first virtual address, first virtual memory identifier (VMID), and first virtual function identifier (VFID).”, paragraph 0019; “first translation lookaside buffer (TLB), wherein the first TLB comprises a cache of entries storing virtual-to-physical address translations”, claim 1; “In one embodiment, the index 310B portion of virtual address, VMID 315, and VFID 320 are utilized as the cache index 325 to locate a given index of cache 330.”, paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hun with Smith such that the address mapping corresponds to a virtual function in order to efficiently virtualize PCIe devices.
Claims 6, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hunt (US 2012/0215979) in view of Chen et al. (“A Simulation Based Study of TLB Performance”).
In regards to claims 6, 13, and 19, Hunt further teaches that responsive to an address mapping being unavailable in the plurality of entries of the TLB, the method further comprises:
storing, by the circuitry in a selected entry of the TLB, an address mapping and metadata that indicates that the address mapping is of the first type (“In another embodiment, for example, if the processor is searching for a TLB entry and the search results in a cache miss, the processor 100 may then search through the cache 110 for a related index 124 with a PDC tag. If the PDC search results in a cache hit, cache 110 returns the physical address of a page table (which is in memory) which includes the desired physical address. The physical address can then be stored in the cache 110 with a TLB tag in the tag array 120.”, paragraph 0033).
Hunt fails to teach that responsive to an address mapping being unavailable in the plurality of entries of the TLB, the method further comprises:
retrieving, by the circuitry, an address mapping from a given entry of a second TLB, wherein each entry of the second TLB stores an address mapping of a first type; and
storing, by the circuitry in a selected entry of the TLB, the address mapping from the given entry of the second TLB.
Chen teaches that responsive to an address mapping being unavailable in the plurality of entries of the TLB (“On a miss, the micro-TLB is reloaded from the shared TLB.”, section 1, paragraph 2), the method further comprises:
retrieving, by the circuitry, an address mapping from a given entry of a second TLB, wherein each entry of the second TLB stores an address mapping of a first type (“On a miss, the micro-TLB is reloaded from the shared TLB.”, section 1, paragraph 2); and
storing, by the circuitry in a selected entry of the TLB, the address mapping from the given entry of the second TLB (“On a miss, the micro-TLB is reloaded from the shared TLB.”, section 1, paragraph 2)
in order to reduce the penalty for a micro-TLB miss (section 1, paragraph 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hunt with Chen such that responsive to an address mapping being unavailable in the plurality of entries of the TLB, the method further comprises:
retrieving, by the circuitry, an address mapping from a given entry of a second TLB, wherein each entry of the second TLB stores an address mapping of a first type; and
storing, by the circuitry in a selected entry of the TLB, the address mapping from the given entry of the second TLB
in order to reduce the penalty for a micro-TLB miss (id.).
Claims 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hunt (US 2012/0215979) in view of Chen et al. (“A Simulation Based Study of TLB Performance”) and Malyugin et al. (US 2010/0318762).
In regards to claims 7, 14, and 20, Hunt in view of Chen teaches claims 6, 13, and 19. Hunt in view of Chen fails to teach that the first type of address mapping corresponds to a guest virtual address to a physical address in a system memory. Malyugin teaches that the first type of address mapping corresponds to a guest virtual address to a physical address in a system memory (“These prior patents and applications describe ‘shadow page tables’ generated by virtualization software and used by a MMU to translate guest virtual addresses (e.g. LPN 406) into machine addresses (e.g. MPN 410).”, paragraph 0010). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hunt with Chen and Malyugin such that the first type of address mapping corresponds to a guest virtual address to a physical address in a system memory in order to reduce the number of translations needed.
Response to Arguments
Applicant's arguments filed 31 July 2025 have been fully considered but they are not persuasive.
While some embodiments of Hunt might be considered a general-purpose cache, Hunt also clearly describes embodiments where only three types of entries are present: standard TLB entries, PDC data, and guest TLB entries (paragraph 0030). Thus, in these embodiments, Hunt is disclosing a TLB dedicated for storage of address translations. Page directory entries are types of address translations. Hunt teaches “A PDC entry has a tag 124 formed from a sub-set of the virtual address and a data type 126 which indicates that the entry is a PDC entry and what level or levels of the page walk the entry represents. The data array entry 132 for a given PDC entry is the physical address of the next step of the page walk which must be performed to complete the translation of the supplied virtual address to the final physical address which is sought.” (paragraph 0022).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 12 February 2026