DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Response to Arguments
3. Applicant’s argument filed on 02/25/2025 with respect claims 1, 8, 14, and 20 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of " operating a test control circuit in response to a first mode and a first set of configuration settings." As recited in claim 1, and similar feature in claims 8, 14, and 20.
Examiner respectfully disagrees since the claims are to be given their broadest reasonable interpretation (BRI) construction in light of the specification (MPEP 2111). Claim 1 is extremely broad and there is no specific feature of what the “first mode” and “first set of configuration settings are? Therefore, the Examiner respectfully disagrees and asserts that Walker et al. (US 2006/0132165 A1) in abstract and paragraph [0004] and claim 1 teaches the such limitation. For example, in accordance with an aspect of the disclosure, a semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronic (PE) stage for producing an AC test signal for testing the semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device under test. Claim 1 recites “a semiconductor device tester, comprising: a PMU stage configured to produce a DC test signal for testing a semiconductor device; a PE stage configured to produce an AC test signal for testing the semiconductor device; and a driver circuit configured to provide, in a first mode, a version of the DC test signal to the semiconductor device and, in a second mode, configured to provide a version of the AC test signal to the semiconductor device.” As been described above, it’s clear that Walker teaches first mode and a first set of configuration settings. The Examiner equates Walker’s " DC test signal" to Applicant's "a first mode" and Walker’s "pin electronic (PE) stage for producing an AC test signal " to Applicant's " first set of configuration settings." Also, Walker clearly states in claim 1 that the driver circuit configured to provide, in a first mode, a version of the DC test signal to the semiconductor device and, in a second mode, configured to provide a version of the AC test signal to the semiconductor device. Emphases added.
Also, the applicant contends that the cited references fail to teaches or suggest the limitation of “receiving, in the test control circuit, a transition trigger signal and state information indicating a second mode and a second set of configuration settings.” As recited in claim 1, and similar feature in claims 8, 14, and 20.
The Examiner respectfully disagrees and asserts that Walker et al. (US 2006/0132165 A1) in paragraphs [0005], [0008], and claim 1 teaches the such limitation. For example, in one embodiment, the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device. The driver circuit may amplify current of the DC test signal produced by the PMU stage and the AC test signal produced by the PE stage. The PMU stage may include a switch that provides another DC test signal to the output stage. See paragraph [0005]. In accordance with another aspect, a method of providing test signals to a semiconductor device includes producing an DC test signal with a PMU stage, amplifying current of the DC test signal with a driver circuit that amplifies an AC test signal from a PE stage, and sending the amplified DC test signal through an output stage to the semiconductor device under test. The output stage is also provides an amplified AC test signal from the PE stage to the semiconductor device. See paragraph [0008]. Further, the applicant contends that the cited references fail to teaches or suggest the limitation of “transition trigger signal and state information indicating a second mode and a second set of configuration settings.” As recited in claim 1, and similar feature in claims 8, 14, and 20. The Examiner respectfully disagrees and asserts that Walker et al. (US 2006/0132165 A1) in paragraphs [0005] and [0009] teaches the such limitation. For example, the driver circuit may amplify current of the DC test signal produced by the PMU stage and the AC test signal produced by the PE stage. The PMU stage may include a switch that provides another DC test signal to the output stage. See paragraph [0005].providing test signals to the semiconductor device may further include passing another DC test signal through a switch and sending this DC test signal through the output stage to the semiconductor device under test. See paragraph [0009]. Furthermore, applicant contends that the cited references fail to teach the limitation of “wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.” As recited in claim 1, and similar feature in claims 8, 14, and 20. The Examiner respectfully disagrees and asserts that Dinteman et al. (US 6,057,716 A) teaches the such limitation. For example, the present invention relates a drive circuit for an integrated circuit (IC) tester. In accordance with one aspect of the invention the drive circuit has two modes of operation: drive and termination. In the drive mode of operation, the drive circuit transmits a differential test signal to terminals of an integrated circuit device under test (DUT) through a matching pair of transmission lines. When the same pair of transmission lines are used to convey a DUT output signal back to the IC tester, the drive circuit operating in its termination mode provides proper termination for the transmission line and provides proper loading for the DUT output signal. With the load at the tester end of each transmission line properly adjusted, the DUT is able to produce its output signal under its specified load conditions. See column 2, lines 20-30.FIG. 1 illustrates in combined block and schematic diagram form, a pin electronics circuit 10 for an integrated circuit tester. Pin electronics circuit 10 includes a drive circuit 12 in accordance with a first embodiment of the present invention and a conventional compare circuit 14. In accordance with the present invention, drive circuit 12 is capable of operating in either of two modes. When an input INHIBIT data bit is low, drive circuit 12 enters a "drive" mode of operation in which it produces an output differential test signal (TEST) of a state determined the state of an input differential DRIVE signal. A pair of transmission lines 16A and 16B deliver the TEST signal to a pair of input/output (I/O) terminals 18A and 18B of an integrated circuit device under test (DUT) 20. The high and low levels of the differential TEST signal are set by input data D.sub.HIGH and D.sub.LOW. When the INHIBIT bit is high, drive circuit 12 enters a "termination" mode of operation. In this mode of operation, while comparing circuit 14 samples the state of a differential output signal DUT.sub.--OUT produced by the DUT 20 on transmission lines 16A and 16B, drive circuit 12 terminates transmission lines 16A and 16B with their characteristic impedances and provides an adjustable load voltage to the DUT.sub.-- OUT signal. Input data D.sub.TERM sets the magnitude of that adjustable load. Current Source Switching Drive Circuit. See column 3, lines 31-55. Finally, the applicant contends that the office action does not establish a proper prima facie case of obviousness. the examiner recognizes that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071,5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992). In this case, the reference of Dintemanin in the same the field of endeavor teaches wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode (see the office action pages 9-10) which is required by the first reference Walker. Second reference Dintemanin explicitly teaches the allowed mode changes in the system of the First reference Walker to improve the test system performance. One of ordinary skill in the art would have recognized the allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode would have improved the test system performance. Therefore, it would have been obvious to one of ordinary skill in the art that Walker and Dinteman as combined teaches the subject matter of claims 1, 8, 14, and 20. See the 35 USC § 103 rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claims 1-5, 8, 9, 11-15, and 17-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Walker et al. (US 2006/0132165 A1) "herein after as Walker" in view of Dinteman et al. (US 6,057,716 A) "herein after as Dinteman."
As per claim 1:
Walker substantially teaches or discloses a method comprising: operating a test control circuit in response to a first mode and a first set of configuration settings (see abstract, paragraph [0004], herein a semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronic (PE) stage for producing an AC test signal for testing the semiconductor device, and Fig. 1); receiving, in the test control circuit, a transition trigger signal and state information indicating a second mode and a second set of configuration settings (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device; and claim 1 “a driver circuit configured to provide, in a first mode, a version of the DC test signal to the semiconductor device and, in a second mode, configured to provide a version of the AC test signal to the semiconductor device); and transitioning the test control circuit, in response to receiving the transition trigger signal, from operating in response to the first mode to operating in response to the second mode by performing allowed mode changes (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device, paragraph [0009], providing test signals to the semiconductor device may further include passing another DC test signal through a switch and sending this DC test signal through the output stage to the semiconductor device under test; and Fig. 5).
Walker does not explicitly teach wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.
However, Dinteman in the same the field of endeavor teaches wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode (see column 2, lines 21-29, herein the drive circuit has two modes of operation: drive and termination. In the drive mode of operation, the drive circuit transmits a differential test signal to terminals of an integrated circuit device under test (DUT) through a matching pair of transmission lines. When the same pair of transmission lines are used to convey a DUT output signal back to the IC tester, the drive circuit operating in its termination mode provides proper termination for the transmission line and provides proper loading for the DUT output signal, and column 3, lines 1-3, herein invention to provide a drive circuit that can switch quickly between its drive and termination modes with minimal noise in the output signal; and See column 3, lines 36-55, the present invention, drive circuit 12 is capable of operating in either of two modes. When an input INHIBIT data bit is low, drive circuit 12 enters a "drive" mode of operation in which it produces an output differential test signal (TEST) of a state determined the state of an input differential DRIVE signal. A pair of transmission lines 16A and 16B deliver the TEST signal to a pair of input/output (I/O) terminals 18A and 18B of an integrated circuit device under test (DUT) 20. The high and low levels of the differential TEST signal are set by input data D.sub.HIGH and D.sub.LOW. When the INHIBIT bit is high, drive circuit 12 enters a "termination" mode of operation. In this mode of operation). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Walker with the teachings of Dinteman by including allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode would have improved the test system performance.
As per claim 2:
Dinteman teaches that wherein the test control circuit does not drive a test signal to the DUT while the test control circuit is in a DUT non-driving mode (see column 6, lines 61-65, herein In the termination mode of operation, when drive circuit 92 is not needed to produce the TEST signal, the INHIBIT data is set so that switch 114 connects the bases of transistors 94 and 96 to a positive voltage source (+V) and so that switch 114 connects DAC 110 to current source 98).
As per claim 3:
Dinteman teaches that wherein the test control circuit transitions from operating in response to the first mode to operating in response to the second mode along a shortest mode change path according to the allowed mode changes (see column 3, lines 1-3, herein invention to provide a drive circuit that can switch quickly between its drive and termination modes with minimal noise in the output signal).
As per claim 4:
Dinteman teaches that wherein, in a DUT non-driving mode, the test control circuit prevents active or leakage signal transmission from the test control circuit to the DUT, or the test control circuit forces a zero current signal on a line coupling the test control circuit to the DUT (see column 5, lines 56-66, herein When drive circuit 62 is not needed to produce the TEST signal the INHIBIT data is set so that switch 74 delivers V.sub.LOAD to node 72 and so that switch 82 is open. With switch 82 open, the current I.sub.E drawn by current source 68 falls to zero. This produces a nearly zero current through transistors 64 and 66. The load driven by the DUT output signal DUT.sub.-- OUT is primarily a function of the impedance of resistors 69 and 70 and the magnitude of V.sub.LOAD supplied to node 72. The resistance R of resistors 69 and 70 is selected to match the characteristic impedance of the transmission lines connected to drive circuit 62 so that the transmission lines are properly terminated).
As per claim 5:
Walker teaches that wherein the transitioning includes looking up an operating state transition super-set sequence in a lookup table of the test control circuit, and sequencing commands in response to the super-set sequence to transition from operating in response to the first mode and the first set of configuration settings to operating in response to the second mode and the second configuration settings (see paragraph [0059], herein Referring to FIG. 10, a portion of IC chip 325 is shown that includes a PMU stage 485 for performing PMU testing. To initiate sending a PMU test signal to DUT 18, PMU control circuitry 425 sends a DC signal over conducting trace 505 to an input 525 of a driver circuit 545 that conditions (e.g., amplifies) the signal and sends it to an output 565).
As per claim 8:
Walker substantially teaches or discloses a test control circuit comprising (see Fig. 1, semiconductor device tester 12 such as an ATE or other similar testing device): a subsystem configured to output test signals to a device under test (DUT), and to receive and perform measurement of response signals of the DUT (see paragraph [0021], herein test routines may initiate the generating and sending of test signals to the semiconductor device-under-test (DUT) and collecting responses from the DUT. Various types of semiconductor devices may be tested by system 10. In this example, an integrated circuit (IC) chip 18 (e.g., memory chip, microprocessor, analog-to-digital converter, digital-to-analog converter, etc.) is tested as a DUT); and a transition control circuit configured to: operate the test control circuit in response to a first operational state information, the first operational state information indicating a first mode and a first set of configuration settings (see abstract, paragraph [0004], herein a semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronic (PE) stage for producing an AC test signal for testing the semiconductor device, and Fig. 1); receive a transition trigger signal and a second operational state information, the second operational state information indicating a second mode and a second set of configuration settings (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device; and claim 1 “a driver circuit configured to provide, in a first mode, a version of the DC test signal to the semiconductor device and, in a second mode, configured to provide a version of the AC test signal to the semiconductor device); and transition the test control circuit, in response to receiving the transition trigger signal, to operating in response to the second operational state information by performing allowed mode changes (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device, paragraph [0009], providing test signals to the semiconductor device may further include passing another DC test signal through a switch and sending this DC test signal through the output stage to the semiconductor device under test; and Fig. 5).
Walker does not explicitly teach wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.
However, Dinteman in the same the field of endeavor teaches wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode (see column 2, lines 21-29, herein the drive circuit has two modes of operation: drive and termination. In the drive mode of operation, the drive circuit transmits a differential test signal to terminals of an integrated circuit device under test (DUT) through a matching pair of transmission lines. When the same pair of transmission lines are used to convey a DUT output signal back to the IC tester, the drive circuit operating in its termination mode provides proper termination for the transmission line and provides proper loading for the DUT output signal, and column 3, lines 1-3, herein invention to provide a drive circuit that can switch quickly between its drive and termination modes with minimal noise in the output signal; and See column 3, lines 36-55, the present invention, drive circuit 12 is capable of operating in either of two modes. When an input INHIBIT data bit is low, drive circuit 12 enters a "drive" mode of operation in which it produces an output differential test signal (TEST) of a state determined the state of an input differential DRIVE signal. A pair of transmission lines 16A and 16B deliver the TEST signal to a pair of input/output (I/O) terminals 18A and 18B of an integrated circuit device under test (DUT) 20. The high and low levels of the differential TEST signal are set by input data D.sub.HIGH and D.sub.LOW. When the INHIBIT bit is high, drive circuit 12 enters a "termination" mode of operation. In this mode of operation). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Walker with the teachings of Dinteman by including allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode would have improved the test system performance.
As per claim 9:
Dinteman teaches that wherein the test control circuit is configured to not drive a signal to the DUT while the test control circuit is in the DUT non-driving mode (see column 6, lines 61-65, herein In the termination mode of operation, when drive circuit 92 is not needed to produce the TEST signal, the INHIBIT data is set so that switch 114 connects the bases of transistors 94 and 96 to a positive voltage source (+V) and so that switch 114 connects DAC 110 to current source 98).
As per claim 11:
Dinteman teaches that wherein the test control circuit includes a driving prevention circuit, the driving prevention circuit configured to: drive a zero current signal to the DUT; or use negative feedback to reduce a leakage signal from an open switch of the test control circuit adapted to couple an output of the test control circuit to an input of the DUT (see column 5, lines 56-66, herein When drive circuit 62 is not needed to produce the TEST signal the INHIBIT data is set so that switch 74 delivers V.sub.LOAD to node 72 and so that switch 82 is open. With switch 82 open, the current I.sub.E drawn by current source 68 falls to zero. This produces a nearly zero current through transistors 64 and 66. The load driven by the DUT output signal DUT.sub.-- OUT is primarily a function of the impedance of resistors 69 and 70 and the magnitude of V.sub.LOAD supplied to node 72. The resistance R of resistors 69 and 70 is selected to match the characteristic impedance of the transmission lines connected to drive circuit 62 so that the transmission lines are properly terminated).
As per claim 12:
Walker teaches that wherein the control circuit includes a lookup table configured to store multiple operating state transition super-set sequences, different operating state transition super-set sequences corresponding to different possible mode change paths according to the allowed mode changes (see paragraph [0059], herein Referring to FIG. 10, a portion of IC chip 325 is shown that includes a PMU stage 485 for performing PMU testing. To initiate sending a PMU test signal to DUT 18, PMU control circuitry 425 sends a DC signal over conducting trace 505 to an input 525 of a driver circuit 545 that conditions (e.g., amplifies) the signal and sends it to an output 565).
As per claim 13:
Walker teaches that wherein the transition control circuit includes an execution circuit configured to translate an operating state transition super-set sequence into a sequence of control signals for controlling the subsystem (see paragraph [0045], herein to initiate a PMU test with PE stage 340, PE control circuitry 500 sends a control signal over conductor 540 to a current test signal generator 56 that is included in PE stage 340. Typically current test signal generator 560 uses the control signal for setting the current level of an output signal that is sent to the DUT).
As per claim 14:
Walker substantially teaches or discloses an automatic test equipment (ATE) comprising (see Fig. 1, semiconductor device tester 12 such as an ATE or other similar testing device): multiple test control circuits, ones of the test control circuits comprising: a subsystem configured to output test signals to one of multiple devices under test (DUTs), and to receive and perform measurement of response signals of the DUT, different ones of the test control circuit corresponding to different ones of the DUTs (see paragraph [0021], herein test routines may initiate the generating and sending of test signals to the semiconductor device-under-test (DUT) and collecting responses from the DUT. Various types of semiconductor devices may be tested by system 10. In this example, an integrated circuit (IC) chip 18 (e.g., memory chip, microprocessor, analog-to-digital converter, digital-to-analog converter, etc.) is tested as a DUT); a transition control circuit configured to: operate the test control circuit in response to a first operational state, the first operational state indicating a first mode and a first set of configuration settings (see paragraph [0022], herein to provide test signals and collect responses from the DUT, semiconductor device tester 12 is connected to one or more connector pins that provide an interface for the internal circuitry of IC chip 18. To test some DUTs, as many as 64 or 128 connector pins may be interfaced to tester 12); receive a transition trigger signal and a second operational state, the second operational state indicating a second mode and a second set of configuration settings (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device; and claim 1 “a driver circuit configured to provide, in a first mode, a version of the DC test signal to the semiconductor device and, in a second mode, configured to provide a version of the AC test signal to the semiconductor device); and transition the test control circuit, in response to receiving the transition trigger signal, to operating the test control circuit in response to the second operational state by performing allowed mode changes (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device, paragraph [0009], providing test signals to the semiconductor device may further include passing another DC test signal through a switch and sending this DC test signal through the output stage to the semiconductor device under test; and Fig. 5); and an interface communication circuit coupled to control the test control circuits, the interface communication circuit configured to provide corresponding transition trigger signals and second operational states to respective ones of the test control circuits (see Fig. 1).
Walker does not explicitly teach wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.
However, Dinteman in the same the field of endeavor teaches wherein allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode(see column 2, lines 21-29, herein the drive circuit has two modes of operation: drive and termination. In the drive mode of operation, the drive circuit transmits a differential test signal to terminals of an integrated circuit device under test (DUT) through a matching pair of transmission lines. When the same pair of transmission lines are used to convey a DUT output signal back to the IC tester, the drive circuit operating in its termination mode provides proper termination for the transmission line and provides proper loading for the DUT output signal, and column 3, lines 1-3, herein invention to provide a drive circuit that can switch quickly between its drive and termination modes with minimal noise in the output signal; and See column 3, lines 36-55, the present invention, drive circuit 12 is capable of operating in either of two modes. When an input INHIBIT data bit is low, drive circuit 12 enters a "drive" mode of operation in which it produces an output differential test signal (TEST) of a state determined the state of an input differential DRIVE signal. A pair of transmission lines 16A and 16B deliver the TEST signal to a pair of input/output (I/O) terminals 18A and 18B of an integrated circuit device under test (DUT) 20. The high and low levels of the differential TEST signal are set by input data D.sub.HIGH and D.sub.LOW. When the INHIBIT bit is high, drive circuit 12 enters a "termination" mode of operation. In this mode of operation). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Walker with the teachings of Dinteman by including allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode would have improved the test system performance.
As per claim 15:
Dinteman teaches that wherein ones of the test control circuits are configured to not drive a signal to the DUT while respective test control circuits are in the DUT non-driving mode(see column 6, lines 61-65, herein In the termination mode of operation, when drive circuit 92 is not needed to produce the TEST signal, the INHIBIT data is set so that switch 114 connects the bases of transistors 94 and 96 to a positive voltage source (+V) and so that switch 114 connects DAC 110 to current source 98).
As per claim 17:
Dinteman teaches that wherein ones of the test control circuits include a driving prevention circuit, the driving prevention circuit configured to: drive a zero current signal to the DUT; or use negative feedback to reduce a leakage signal from an open switch of the test control circuit adapted to couple an output of the test control circuit to an input of the DUT (see column 5, lines 56-61, herein When drive circuit 62 is not needed to produce the TEST signal the INHIBIT data is set so that switch 74 delivers V.sub.LOAD to node 72 and so that switch 82 is open. With switch 82 open, the current I.sub.E drawn by current source 68 falls to zero. This produces a nearly zero current through transistors 64 and 66).
As per claim 18:
Walker teaches that wherein ones of the control circuit include a lookup table configured to store multiple operating state transition super-set sequences, different ones of the operating state transition super-set sequences corresponding to each possible mode change path, wherein the possible mode change paths include a minimum number of mode changes and accord with the allowed mode changes (see paragraph [0059], herein Referring to FIG. 10, a portion of IC chip 325 is shown that includes a PMU stage 485 for performing PMU testing. To initiate sending a PMU test signal to DUT 18, PMU control circuitry 425 sends a DC signal over conducting trace 505 to an input 525 of a driver circuit 545 that conditions (e.g., amplifies) the signal and sends it to an output 565).
As per claim 19:
Walker teaches that wherein the transition control circuit includes an execution circuit configured to translate an operating state transition super-set sequence into a sequence of control signals for controlling the subsystem (see paragraph [0045], herein to initiate a PMU test with PE stage 340, PE control circuitry 500 sends a control signal over conductor 540 to a current test signal generator 56 that is included in PE stage 340. Typically current test signal generator 560 uses the control signal for setting the current level of an output signal that is sent to the DUT).
As per claim 20:
Walker substantially teaches or discloses a test control circuit comprising (see Fig. 1, semiconductor device tester 12 such as an ATE or other similar testing device): a subsystem configured to output test signals to a device under test (DUT), and to receive and perform measurement of response signals of the DUT (see paragraph [0021], herein test routines may initiate the generating and sending of test signals to the semiconductor device-under-test (DUT) and collecting responses from the DUT. Various types of semiconductor devices may be tested by system 10. In this example, an integrated circuit (IC) chip 18 (e.g., memory chip, microprocessor, analog-to-digital converter, digital-to-analog converter, etc.) is tested as a DUT); a memory storing multiple sets of sequenced operational state transition commands, and configured to store a first operational state information and a second operational state information (see paragraph [0024], herein IC chip 36 may initiate transmitting a vector of binary values to the DUT for storing on the DUT. Once stored, the DUT is accessed by tester 12 to determine if the correct binary values have been stored); and a transition control circuit configured to: operate the test control circuit in response to the first operational state information, the first operational state information indicating a first mode and a first set of configuration settings (see paragraph [0022], herein to provide test signals and collect responses from the DUT, semiconductor device tester 12 is connected to one or more connector pins that provide an interface for the internal circuitry of IC chip 18. To test some DUTs, as many as 64 or 128 connector pins may be interfaced to tester 12); receive a transition trigger signal (see paragraph [0004], herein A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device under test, and Fig. 1); transition the test control circuit, in response to receiving the transition trigger signal, to operating in response to the second operational state information, the second operational state information indicating a second mode and a second set of configuration settings (see paragraph [0005], herein the semiconductor device tester may include of an output stage for providing the versions of the test signals from the driver circuit to the semiconductor device, paragraph [0009], providing test signals to the semiconductor device may further include passing another DC test signal through a switch and sending this DC test signal through the output stage to the semiconductor device under test; and Fig. 5); wherein different ones of the sets of sequenced operational state transition commands correspond to different combinations of the first mode and the second mode (see paragraph [0024], herein IC chip 36 may initiate transmitting a vector of binary values to the DUT for storing on the DUT. Once stored, the DUT is accessed by tester 12 to determine if the correct binary values have been stored).
Walker does not explicitly teach wherein the transition action includes transitioning the test control circuit from operating in response to the first mode and the first configuration settings, to operating in response to the second mode and the second configuration settings, in an order responsive to the set of sequenced operational state transition commands corresponding to the first mode and the second mode.
However, Dinteman in the same the field of endeavor teaches wherein the transition action includes transitioning the test control circuit from operating in response to the first mode and the first configuration settings, to operating in response to the second mode and the second configuration settings, in an order responsive to the set of sequenced operational state transition commands corresponding to the first mode and the second mode (see column 2, lines 21-29, herein the drive circuit has two modes of operation: drive and termination. In the drive mode of operation, the drive circuit transmits a differential test signal to terminals of an integrated circuit device under test (DUT) through a matching pair of transmission lines. When the same pair of transmission lines are used to convey a DUT output signal back to the IC tester, the drive circuit operating in its termination mode provides proper termination for the transmission line and provides proper loading for the DUT output signal, and column 3, lines 1-3, herein invention to provide a drive circuit that can switch quickly between its drive and termination modes with minimal noise in the output signal; and See column 3, lines 36-55, the present invention, drive circuit 12 is capable of operating in either of two modes. When an input INHIBIT data bit is low, drive circuit 12 enters a "drive" mode of operation in which it produces an output differential test signal (TEST) of a state determined the state of an input differential DRIVE signal. A pair of transmission lines 16A and 16B deliver the TEST signal to a pair of input/output (I/O) terminals 18A and 18B of an integrated circuit device under test (DUT) 20. The high and low levels of the differential TEST signal are set by input data D.sub.HIGH and D.sub.LOW. When the INHIBIT bit is high, drive circuit 12 enters a "termination" mode of operation. In this mode of operation). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Walker with the teachings of Dinteman by including transitioning the test control circuit from operating in response to the first mode and the first configuration settings, to operating in response to the second mode and the second configuration settings, in an order responsive to the set of sequenced operational state transition commands corresponding to the first mode and the second mode. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the test control circuit from operating in response to the first mode and the first configuration settings, to operating in response to the second mode and the second configuration settings, in an order responsive to the set of sequenced operational state transition commands corresponding to the first mode and the second mode would have improved the test system performance.
Allowable Subject Matter
5. Claims 6, 10, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claim 7 depend from on claim 6 and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
6. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
7. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
8. THIS ACTION IS MADE FINAL; Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/OSMAN ALSHACK/
Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
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