Prosecution Insights
Last updated: October 01, 2026
Application No. 18/478,921

HIGH POWER LASER ARRAY DEVICES AND METHODS

Non-Final OA §103
Filed
Sep 29, 2023
Priority
Jul 22, 2019 — provisional 62/876,919 +1 more
Examiner
CARTER, MICHAEL W
Art Unit
2828
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
II-VI Delaware Inc.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
642 granted / 864 resolved
+6.3% vs TC avg
Strong +16% interview lift
Without
With
+15.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
21 currently pending
Career history
888
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
56.6%
+16.6% vs TC avg
§102
17.8%
-22.2% vs TC avg
§112
21.1%
-18.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 864 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of the invention of group 1, claims 5-21, in the reply filed on 6/17/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-14, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0128375 (Kimoto) in view of US 2004/0175852 (Ooi). For claim 5, Kimoto teaches a method of manufacturing an optoelectronic assembly (fig. 1), the method comprising: forming a multimode interference coupler (fig. 1 and 3, label 13; [0033] and [0074]) on a substrate (fig. 3, 21; [0035]); wherein forming the multimode interference coupler comprises: the multimode interference coupler (fig. 1, 13 (B-B), and fig. 3) is formed between other regions of the quantum well and barrier layer (formed between a first region shown in fig. 1, 11-1 to11-n (A-A) and fig. 2, 24a and a second region shown in fig. 1, 14 (C-C) and fig. 4, 24b) and providing a laser array (fig. 1 and 2, label11-1 to 11-n; [0033]) on the substrate (fig. 2, 21) including optically coupling the laser array and the multimode interference coupler (fig. 1, 12-1 to 12-n; [0038]). Kimoto does not teach forming the multimode interference coupler comprises: depositing a quantum well and barrier layer on a substrate; and annealing the quantum well and barrier layer, the multimode interference region having a band gap that is different from the band gap of the other regions of the quantum well and barrier layer. However, Ooi teaches a method of forming a passive device such as a multimode interference coupler ([0003]) may be formed by depositing a quantum well and barrier layer (fig. 4-5C, 206/208) on a substrate (fig. 4-5C, 212); and annealing the quantum well and barrier layer ([0022], fig. 5C; [0077]), the passive device having a band gap that is different from the band gap of the other regions of the quantum well and barrier layer [0077] in order to form a monolithic integrated device which does not require regrowth providing a simplified technique ([0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ooi’s method of forming a passive device to form the passive multimode interference coupler of Kimoto in order to form a monolithic integrated device which does not require regrowth providing a simplified fabrication technique. For claim 6, Kimoto teaches comprising selecting, before forming the multimode interference coupler, a range of wavelengths of laser light to be emitted by the laser array (fig. 9; [0064]-[0065]; the range of wavelengths is selected by the choice of active layers material and DFB grating prior to the formation of the coupler in fig. 10-11). The combination of Kimoto and Ooi inherently teach the multimode interference region is configured to absorb less of the range of wavelengths of laser light than the other regions of the quantum well and barrier layer. (Quantum well intermixing creates a larger bandgap compared to the quantum wells, and, as a result, absorb less of the range of wavelengths of laser light. See [0008] of Ooi). For claim 7, Ooi teaches the passive region (i.e. the multimode interference region of the combination) is transparent to the range of wavelengths of the laser light ([0004]). For claim 8, Ooi teaches forming the multimode interference coupler further comprises depositing a buffer layer (fig. 4 and 5A, 222) on the quantum well and barrier layer (fig. 4 and 5A, 226) before annealing the quantum well and barrier layer ( between fig. 5B and fig. 5C; [0076]). For claim 9, Ooi teaches forming the multimode interference coupler further comprises depositing a cap layer on the buffer layer before annealing the quantum well and barrier layer (fig. 5A, 228). For claim 10, Ooi teaches forming the multimode interference coupler further comprises directing ions at the buffer layer after depositing the cap layer and before annealing the quantum well and barrier layer (fig. 5B, [0073]). For claim 11, Ooi teaches the cap layer (fig. 5A, 228) is deposited on the buffer layer above the other regions of the quantum well and barrier layer (fig. 5A, above 222 and 226) and the buffer layer comprises an exposed surface without the cap layer deposited thereon (fig. 5A, 230). For claim 12, Ooi teaches the cap layer comprises silicon nitride ([0043]). For claim 13, Ooi teaches the multimode interference region formed during the annealing of the quantum well and barrier layer is directly below the exposed surface of the buffer layer (fig. 5C, 238; [0078]). For claim 14, Ooi teaches the ions comprise phosphorus ions ([0073]). For claim 17, Kimoto further teaches forming a spot size converter region (fig. 1, 15). As discussed in the rejection of claim 5 above, Ooi teaches annealing the quantum well and barrier layer in order to form a monolithic integrated device which does not require regrowth providing a simplified technique. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ooi’s method of forming a passive device to form the passive spot size converter of Kimoto in order to form a monolithic integrated device which does not require regrowth providing a simplified fabrication technique. For claim 21, Ooi teaches annealing the quantum well and barrier layer to form a multimode interference region between other regions of the quantum well and barrier layer causes diffusion of vacancies in the quantum well and barrier layer ([0019]). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0128375 (Kimoto) in view of US 2004/0175852 (Ooi) and US 2002/0072142 (Ooi 142). For claim 15, the previous combination does not teach removing the cap layer from the buffer layer after annealing the quantum well and barrier layer. However, Ooi 142 teaches the cap layer (the implant mask) may be removed or left on for annealing ([0086]). Ooi 142 further teaches removing the capping layer after annealing ([0170]) in order to prepare the device for patterning ([0171]-[0173]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to leave the cap layer on for annealing as a known alternative to removing it before annealing in the previous combination as taught by Ooi 142 and then removing it after annealing in order to prepare the device for patterning. The modification of the previous combination has the advantage of reducing the steps required by not requiring the pre-anneal removal. Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0128375 (Kimoto) in view of US 2004/0175852 (Ooi) and US 2015/0063740 (Gotoda). For claim 18, Kimoto further teaches an amplifier (fig. 1, 14; [0039] and fig. 4) on the substrate (fig. 4, 21) including optically coupling the amplifier to an outlet of the multimode interference coupler (fig. 1, 13). Kimoto does not teach the amplifier is an amplifier array. However, Gotoda teaches a similar device (fig. 1) which includes an amplifier array (fig. 1, 22 and 23; [0063]) coupled to an outlet side of a MMI coupler (fig. 1, 21; [0063]) in order to provide two outputs with different amplification ([0073]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an amplifier array as taught by Gotoda in the previous combination in order to provide two outputs with different amplification. For claim 19, Gotoda further teaches optically coupling a lens (fig. 9, 16) to the amplifier array (fig. 9, 30; [0127]-[0137], “output ports of the wavelength variable source”); optically coupling a fiber array to the lens (fig. 9, 17; [0128]). The combination does not teach the lens is a lens array and optically coupling an isolator to and between the lens array and the fiber array. However, the examiner takes official notice that lens arrays were well-known in the art before the filing date of the claimed invention for coupling amplifier arrays to fiber arrays and isolators were well-known in the art before the filing date of the claimed invention in order to prevent spurious feedback between lenses and amplifiers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the well-known lens array and isolator with the previous combination in order to couple the amplifier array to the fiber array and to prevent spurious feedback between lenses and amplifiers. For claim 20, the examiner took official notice int the rejection of claim 19 above the isolators were well-known for preventing feedback. The combination of Kimoto, Ooi, Gotoda with a well-known isolator as described in the rejection of claim 19 has the isolator configured to allow unidirectional travel of laser light from the lens array to the fiber array as it prevents spurious feedback. Allowable Subject Matter Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2008/0226229 teaches an amplifier array coupled to a fiber array using a lens array. US 2005/0185262 teaches an isolator used in a fiber coupling arrangement. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael W Carter whose telephone number is (571)270-1872. The examiner can normally be reached M-F, 9:00-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael Carter/ Primary Examiner, Art Unit 2828
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Prosecution Timeline

Sep 29, 2023
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
90%
With Interview (+15.8%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 864 resolved cases by this examiner. Grant probability derived from career allowance rate.

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