Prosecution Insights
Last updated: August 16, 2026
Application No. 18/479,093

PHASE SHIFTER AND PHASE SHIFTING METHOD

Non-Final OA §103
Filed
Oct 01, 2023
Priority
Sep 23, 2021 — CN 202111116105.X +1 more
Examiner
RAHMAN, HAFIZUR
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Smarter Microelectronics (Guang Zhou) Co. Ltd.
OA Round
2 (Non-Final)
94%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
693 granted / 741 resolved
+25.5% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
40 currently pending
Career history
765
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.9%
+4.9% vs TC avg
§102
35.4%
-4.6% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 741 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Finality of the Action Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Response to Arguments Applicant's remarks filed on May 22, 2026, have been fully considered. However, the arguments presented therein are unpersuasive to overcome the rejections of record. Applicant argues that the present disclosure introduces a controller that generates control signals based on the real-time frequency of the input RF signal, which directly adjusts the circuit impedance inside the quadrature signal generator (e.g., adjusting the delay constant of the RC phase-shifting circuit). Applicant further argues that this represents a frequency-based adaptive reconstruction that ensures accurate quadrature signals at different frequencies, whereas Kang only teaches controlling the amplitude of two signals through a power distribution unit. However, the Examiner respectfully points out that the features argued by the Applicant—specifically "real-time frequency" dependence and "adjusting the circuit impedance"—are completely absent from the amended claim language. The amendments to independent claims 1, 14, and 15 strictly add the limitation: "wherein the adder is controlled by a control signal generated by a controller based on a preset phase shift angle". Limitations not recited in the claims cannot be read into them to overcome prior art. Regarding the newly claimed limitation, Kang discloses that four paths of orthogonal signals are input to the signal combining unit U5, and these signals are combined using a control signal. Kang explicitly teaches rationally selecting the combined signal of the polar and its size to obtain an output signal of any phase. As already established in the previous Office Action, the automation of such electronic control signals using a controller (such as a microprocessor) based on a preset or desired phase angle is a routine design choice. Therefore, the amendments do not render the claims patentable. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-5, and 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (CN 105207644 B, “Active Phase Shifter Based on Vector Synthesis on Sheet,” filed 16 Sep 2015; published 21 Aug 2018) in view of Common Control Algorithm Knowledge. Regarding claim 1, Kang discloses a phase shifter comprising An orthogonal signal generator connected to an adder (Quadrature (orthogonal) signal generating unit U2 (FIG. 1; p. 4 ll. 30–36) — “generates orthogonal  I, Q  two  signals  composed  of  a low-pass network  and  a  T-type  high-pass”  The  output  of  U2  is  connected  to  the  signal synthesizing unit U5 (p. 4 ll. 36–41)). Wherein Adder adjusts amplitude and performs vector composition and phase compensation (Signal synthesizing unit U5 (p. 5 ll. 1–10) “comprising a Gilbert cell circuit … having signal amplifying function of polar selection and signal synthesis.” Further (p. 4 ll. 8–13) — “by rationally selecting the combined signal of the polar and the size thereof so as to obtain an output signal of any phase.” This explicitly teaches amplitude adjustment and vector-additive phase composition.) The signal synthesizing unit U5 acts as the adder and performs signal synthesis and amplitude adjustment. Kang teaches that four paths of orthogonal signals are input to the signal combining unit U5, and they are combined using a control signal to obtain an output signal of any phase. PNG media_image1.png 650 908 media_image1.png Greyscale Fig. 1 of Kang annotated by the examiner for ease of reference. Kang does not explicitly use the exact phrase that the control signal is "generated by a controller based on a preset phase shift angle." However, replacing manual or basic electronic controls with automated digital preset controls, look-up table values, or microprocessors is a routine automation of known analog controls. It would have been obvious to a person of ordinary skill in the art to automate Kang's vector modulator using an automatic control algorithm and a controller to generate the control signal based on a desired or preset phase angle to achieve repeatable and accurate phase settings. Wherein Multiple signal-processing units and adder units (Differential signal generating units U3 and U4 (page 4 ll. 42–47) process and feed their outputs into U5 (page 4, l. 47 – p. 5 l. 3)) Wherein Amplitude-adjustment and phase-compensation units (Power-distribution unit U1 (p. 4 ll. 17–24) performs “gain adjustment and power distribution … outputs two paths of controllable amplitude.” Orthogonal signal generator U2 (p. 4,  ll. 31–36) acts as phase compensation via 90° offset) Wherein Phase-compensation structure π, T or L TYPE (Page 5 ll. 24–29  “The orthogonal signal generating unit is composed of a T-shaped high-pass network and a Π-type (low-pass) network of inductors and capacitors.”) Wherein the Phase-compensation unit adjustable with gain/output power (Page 5 ll. 17–24 demonstrates gain-controlled transistors MS1–MS4 used to change signal amplitude and thus effective phase position, satisfying adaptive adjustment.) Wherein Variable-gain amplifier or differential amplifier (FIG. 2 of Kang shows transistor pairs MA through MS4 forming dielectric-control variable-gain amplifiers; these operate as differential pairs.) Wherein the First phase-shift signal is differential (Repeated at p. 5 ll. 10–16 — “two groups of differential signals input signal synthesizing unit … the output balun converts the differential signal into a single-end output.”) Wherein per Orthogonal signal comprises multi-channel sub-signals (Fig. 1 and text (p. 4 lines 41 – p. 5 line 3) show four sub-signals, VI+, VI−, VQ+, VQ−). Amplifier assembly with two transformers and amplifier (Input and output baluns (FIGS. 1, 3, 4; p. 5 ll. 24–34) function as first and second transformers; the active FET amplifier stages (U3–U5) provide the required power conversion). Regarding amended independent claims 14 and 15, the methods of generating a first orthogonal signal, adjusting amplitude, and performing vector composing to obtain a phase shift signal are disclosed by Kang. The limitation that the adder is controlled by a control signal generated by a controller based on a preset phase shift angle is obvious over Kang in view of Common Control Algorithm Knowledge, as replacing manual control signals with digital preset controls is a routine automation. Regarding claims 16 Kang et al. (p. 3 ll. 35–38; p. 5 ll. 1–11) discloses the use of electronic control signals to select discrete gain and phase states of the FET branches, thereby controlling the phase shift angle.  However, replacing manual control signals with digital preset controls, look-up table values, or real-time feedback is a routine automation of known analog controls are common knowledge in the art where accuracy, predictability and better controls can be ensured. Therefore, it would have been obvious to a person of ordinary skill in the art to establish automatic control algorithm and microprocessor for such automation for Kang’s vector modulator. Thus, automatic generation of the control signal based on a desired phase angle would have been an obvious design choice to a skilled RF-IC and vector modulator designer for achieving repeatable and accurate phase settings. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Katsube et al. (US 2012/0194265 A1). Regarding claim 6, Kang et al. (p. 3 ll. 5–8) explicitly teaches use of inductors and capacitors within the phase-compensation network. While switch elements for changing the effective reactance are not literally disclosed. However, page 3 lines 10–17 states that the Gilbert cell uses “switch control circuits …  for polar selection and signal combination.” Katsube in a similar filed of endeavor of switch control circuit for tunable integrated Phase sifter circuit including step-wise tuning of capacitance or inductance values as standard practice in RF integrated-circuit phase shifters. It would have been obvious to extend such switch control techniques to the reactive elements of the phase network to achieve step-wise tuning of capacitance or inductance values, as is standard practice in RF integrated-circuit phase shifters. The result of such switch-controlled step wise tunable capacitor and inductor is to achieve fine, discrete phase control using switchable LC cells. This would provide predictable yields. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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Prosecution Timeline

Oct 01, 2023
Application Filed
Feb 23, 2026
Non-Final Rejection mailed — §103
May 22, 2026
Response Filed
Jun 09, 2026
Final Rejection mailed — §103
Aug 10, 2026
Response after Non-Final Action
Aug 12, 2026
Examiner Interview (Telephonic)

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Prosecution Projections

2-3
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+8.3%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 741 resolved cases by this examiner. Grant probability derived from career allowance rate.

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