Prosecution Insights
Last updated: May 29, 2026
Application No. 18/479,104

AMPLIFIER ASSEMBLY AND PHASE SHIFTING METHOD

Non-Final OA §102§103§112
Filed
Oct 01, 2023
Priority
Sep 23, 2021 — CN 202111116040.9 +1 more
Examiner
NGUYEN, KHANH V
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Smarter Microelectronics (Guang Zhou) Co. Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1111 granted / 1187 resolved
+25.6% vs TC avg
Minimal +2% lift
Without
With
+1.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
18 currently pending
Career history
1211
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
44.4%
+4.4% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1187 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3-6, 11 and 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 3, recites the limitation "the phase compensation circuit" in lines 1 and 2. There is insufficient antecedent basis for this limitation in the claim. Note, “a phase compensation circuit” is claimed in claim 2. Regarding claim 3, recited “wherein an input end of the phase compensation circuit (304/405) is connected with the output end of the adder (302/402) and an output end of the phase compensation circuit (304/405) is connected with the amplifier (303/404) to output the phase-compensated first signal.” It is noted that submitted drawings (Figs. 3 and 4) disclose an input end of the phase compensation circuit (304/405) is connected to/with the amplifier (303/404) to output the phase compensated signal. Clarification is needed. Regarding claim 4, recites the limitation "the phase compensation circuit" in line 3. There is insufficient antecedent basis for this limitation in the claim. Note, “a phase compensation circuit” is claimed in claim 2. Regarding claim 5, recites the limitation "the phase compensation circuit" in line 1. There is insufficient antecedent basis for this limitation in the claim. Note, “a phase compensation circuit” is claimed in claim 2. Regarding claim 6, recites the limitation "the phase compensation circuit " in line 1. There is insufficient antecedent basis for this limitation in the claim. Note, “a phase compensation circuit” is claimed in claim 2. Regarding claim 11, recites the limitation "the amplifier" in line 1. There is insufficient antecedent basis for this limitation in the claim. Note, “an amplifier” is claimed in claim 2. Regarding claim 17, recited “wherein the first control signal is used for controlling an adder, and the second control signal is used for controlling an amplification circuit; vector-synthesizing an orthogonal signal generated by an orthogonal signal generator through controlling the adder based on the first control signal”. Applicant’s submitting drawings (Figs. 1 and 11) disclose Control Signal has two controlling signal paths for controlling path selecting unit (1031/1103’) and variable gain amplifier (1032/1103), respectively. However, there is no showing of an adder (1033/1103’’) being controlled by either control signals as claimed. Clarification is needed. Regarding claims 18 and 19, also rejected because they depends on rejected claim 17. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 4, 5, 7 and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyashita (6,288,610). Regarding claims 1 and 12, Miyashita (Fig. 17) discloses an amplifier circuit/assembly comprising: a DSP7A, D/A converter (24/25) and multiplier (72) formed an orthogonal signal generator, an adder (73), and an amplification circuit (10); an output end of the orthogonal signal generator being connected with an input end of the adder, and the orthogonal signal generator being configured to generate an orthogonal signal; an output end of the adder (73) being connected with an input end of the amplification circuit (10), and the adder being configured to vector-synthesize the orthogonal signal to output a first signal; and the amplification circuit being configured to amplify a power of the first signal and compensate a phase of the first signal to output a second signal to an antenna (A) or to demodulator (93), see col. 34 ,line 28 to col. 35, line 2. Regarding claim 2, wherein the amplification circuit comprises an amplifier (10) and a phase compensation circuit (2B); the amplifier is configured to amplify the power of the first signal; the phase compensation circuit is configured to compensate the phase of the first signal. Regarding claim 4, wherein an input end of the amplifier (10) is connected with the output end of the adder (73) and an output end of the amplifier is connected with an input end of the phase compensation circuit (2B) to output the amplified first signal. Regarding claim 5, wherein a compensation phase of the phase compensation circuit (2B) is adjustable based on an output power of the amplifier (10) via detecting unit (2A). Regarding claims 7 and 14, wherein the amplifier circuit further comprises demodulator (93), A/D (94) and detecting unit (2A) formed a first isolation circuit having an input end connected with an output end of the amplification circuit, and being configured to isolate the output end of the amplification circuit to isolate an interference of a downstream circuit of the amplification circuit to the amplification circuit. Regarding claim 13, wherein the amplification circuit comprises an amplifier (10) and a phase compensation circuit (2B); correspondingly, the amplifying a power of the first signal and compensating a phase of the first signal by an amplification circuit to output a second signal comprises amplifying the power of the first signal by the amplifier; and compensating the phase of the power-amplified first signal by the phase compensation circuit to output the second signal. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyashita. Regarding claim 11, recited the amplifier is a differential amplifier. Miyashita discloses a single-ended amplifier and not differential amplifier as claimed. However, single-ended/differential amplifier is well-known in the art and utilizing one of known amplifiers is considered a matter of design engineering for specific intended use of the invention. Note, applicant also acknowledged that amplifier can be a single-ended amplifier depend on the number of output(s) from the adder. Allowable Subject Matter Claims 2, 6, 8-10, 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6, prior art(s) does not disclose the phase compensation circuit has a compensation structure of at least one of “pi (π) type”, “T type” and “L type”. Regarding claims 8 and 15, prior art(s) does not disclose the amplifier assembly further comprises a second isolation circuit (306/407), an input end of the second isolation circuit is connected with the output end of the adder, and an output end of the second isolation circuit is connected with the input end of the amplification circuit; and the second isolation circuit is configured to isolate the output of the adder. Regarding claims 9 and 16, prior art(s) does not disclose the amplification circuit further comprises an impedance matching circuit; the impedance matching circuit is configured to impedance-match an input impedance and/or an output impedance and/or an inter-stage impedance of the amplifier. Regarding claim 10, prior art(s) does not disclose the phase compensation circuit comprises at least one of an inductor, a capacitor and a switching tube. Claims 17-19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry having orthogonal signal. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST. Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINDGREN BALTZELL ANDREA can be reached on (571) 272-5918. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application lnformation Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Oct 01, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
96%
With Interview (+1.9%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1187 resolved cases by this examiner. Grant probability derived from career allowance rate.

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