DETAILED ACTION
This office action is in response to the RCE filed on 12/17/2025.
Claims 1-20 are pending in the application and have been examined.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/02/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-8, 11-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesh (U.S. Publication 2018/0165381) in view of Russell (U.S Publication 2011/0302394).
Regarding claims 1 and 13, Venkatesh discloses a method comprising: storing, by a memory, a set of table elements in a memory (Fig. 3, Paragraph 63, each key and each value as an element in CAM 245, all the keys and values as a set of table elements); storing, by a processor core, an index in a register of the= processor core (paragraph 89, register indicated by 512); receiving an instruction, by the processor core (Paragraph 87, gather-update-scatter instruction); and based on the instruction, for the index, performing an arithmetic operation on a respective table element of the set of table elements associated with the respective index (Fig. 5, Paragraph 91).
Venkatesh also teaches performing an arithmetic operation on each index of a set of indices (Paragraph 75). Although Venkatesh teaches iterating through multiple indices and performing an arithmetic operation on multiple data values retrieved using the indices (Paragraph 75), Venkatesh does not teach storing a set of indices in a register. Venkatesh also does not teach performing the arithmetic operation for each index of the set of indices based on the instruction.
Russell teaches a single gather instruction that acts on each index of a set of indices. The instruction gathers data values based on a set of indices (Fig. 7, Paragraph 52), wherein the indices are stored in a register (Fig. 7, Paragraph 52).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement a single gather-update-scatter instruction that acts on each index of a set of indices. This single instruction would gather-update-scatter data values based on the set of indices stored in a register. This would result in a set of indices being stored in a register. As the gather-update-scatter instruction performs an arithmetic operation on a table element, this would also result in the arithmetic operation being performed for each index of the set of indices based on the instruction.
One of ordinary skill in the art would be motivated to do so as it would allow updating multiple values using a single instruction. This would reduce the number of instructions to be fetched, store for scheduling. Storing in registers would allow for rapid access to data thus improving speed of processing.
Regarding claims 6 and 18, Venkatesh in view of Russell discloses the method of claim 13, wherein the instruction specifies the register and the set of table elements. [Venkatesh, paragraphs 75-76, Fig. 2; the instruction specifies registers and a table element; Russell, Fig. 2, paragraph 52; the instruction accesses multiple table elements].
Regarding claims 7 and 19, Venkatesh in view of Russell discloses the method of claim 18, wherein the instruction includes: a first field that specifies the register; and a second field that follows the first field and that specifies the set of table elements [Venkatesh, paragraphs 75-76, Fig. 2; the instruction specifies a register followed by a table element; Russell, Fig. 2, paragraph 52; the instruction accesses multiple table elements].
Regarding claim 8, Venkatesh in view of Russell discloses the device of claim 6, wherein: the register is a first register; the processor core includes a second register configured to store a base address associated with the set of table elements; and the instruction specifies the set of table elements by specifying the second register [Venkatesh, paragraph 0078; a base address is used for accessing data].
Regarding claims 11-12 and 20, Venkatesh in view of Russell discloses the method of claim 19, wherein the memory is a level one (L1) data cache memory [Venkatesh, Fig. 2, paragraphs 66-67; the data is stored in a CAM, which operates as an L1 data cache memory].
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesh in view of Russell and Official Notice.
Regarding claims 2 and 14, Venkatesh in view of Russell discloses the method of claim 13, wherein the arithmetic operation is incrementing the respective table element [Venkatesh, paragraph 0076; a value is added to the value in the table] Venkatesh in view of Russell does not explicitly disclose that the value by which the table value is incremented is one. Instead, Venkatesh indicates that the value may be specified in a memory. The examiner takes official notice that the operation of incrementing a value by 1 was notoriously well known and commonly used in computing applications such as that disclosed by Venkatesh. Given that Venkatesh allows an increment by any specified number stored in memory, a person having skill in the art would have contemplated and understood the benefits of incrementing by one, and the claimed invention would therefore have been obvious.
Allowable Subject Matter
Claims 3-5, 9-10, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corey Faherty whose telephone number is (571)270-1319. The examiner can normally be reached weekdays between 7:30 and 4:00 ET, with every other Friday off.
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/COREY S FAHERTY/Primary Examiner, Art Unit 2183