DETAILED ACTION
This is in response to the application filed on October 2, 2023 in which claims 2 - 34 are presented for examination (after preliminary amendment of 2/22/2024).
Status of Claims
Claims 2 – 34 are pending, of which claims 2, 10, 15, 18, 22, and 27 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements filed 2/22/2024 and 7/2/2025 fail to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because the IDS of 2/22/2024 does not provide Non-Patent Literature document #8 (and it is not found in any parent application) and the IDS of 7/2/2025 lists a single U.S. Patent, but a digit is missing from the patent number. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2 – 7, 10 – 18, 20, and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 3, 5, 7, 12 – 16, 19, 22 – 24, 27, and 28 of U.S. Patent No. 10,365,833 in view of Jalalifar et al., “An Energy-Efficient Mobile PAM Memory Interface for Future 3D Stacked Mobile DRAMs”. Both the instant application and U.S. Patent 10,365,833 claim features of multilevel logic. While the instant application claims a dynamic random access memory (DRAM) comprising the multilevel logic, a DRAM with a PAM interface is known in the art. This is described in Jalalifar. It would have been obvious to utilize the multilevel logic of 10,365,833 in a DRAM interface.
10,365,833
18/479642
1. An apparatus, comprising:
a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals, wherein a count of the plurality of bitstreams is greater than a count of the plurality of multilevel signals, the driver circuit farther configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers, wherein each of the individual drivers is configured to drive more than two voltages, wherein the driver circuit includes a multilevel signal encoder including a plurality of logic circuits,
and each logic circuit of the plurality of logic circuits included in the multilevel signal encoder is configured to input all of the plurality of bitstreams, wherein
the driver circuit is a multi-leg driver that is divided into at least two sections for driving the more than two voltages, wherein each of the at least two sections of the driver circuit
associated with one of the plurality of multilevel signals
is configured to be controlled to drive the plurality of multilevel signals onto respective signal lines, and wherein first and second control signals are used to control respective sections of the plurality of sections of the driver circuit associated with one of the plurality of multilevel signals,
and each of the first and second control signals is generated based on all of the plurality of bitstreams.
2. A dynamic random access memory (DRAM), comprising:
a driver circuit configured to convert a plurality of bits into a plurality of
symbols, wherein a number of the plurality of bits is greater than a
number of the plurality of symbols,
the driver circuit further configured to drive the plurality of symbols
onto a plurality of signal lines using individual drivers, wherein each of the individual drivers is configured to drive more than two voltages, wherein the driver circuit includes a multilevel signal encoder including a plurality of logic circuits, and
the driver circuit is a multi-leg driver that is divided into at least two sections for driving the more than two voltages, wherein each of the at least two sections of the driver circuit
is configured to be controlled to drive the plurality of symbols onto the plurality of signal lines, and wherein first
and second control signals are used to control respective sections of the at least two sections of the driver circuit.
12. An apparatus, comprising:
a receiver and decoder circuit configured to receive a plurality of multilevel signals
and to decode the plurality of multilevel signals to recover a plurality of bitstreams, wherein a count of the plurality of bitstreams is greater than a count of the plurality of multilevel signals, the receiver and decoder circuit configured to use a pair of reference voltages to determine signal levels of each of the plurality of multilevel signals and to decode the plurality of multilevel signals based on the determined multilevel signal levels, and wherein the receiver and decoder circuit includes a plurality of pairs of comparators associated with the plurality of multilevel signals, respectively, a first pair of the plurality of pairs of comparators is configured to input a first multilevel signal of the plurality of multilevel signals and to input the pair of reference voltages, and a second pair of the plurality of pairs of comparators is configured to input a second multilevel signal of the plurality of multilevel signals and to input the pair of reference voltages, and wherein only two reference voltages including the pair of reference voltages are used to determine signal levels of each of the plurality of multilevel signals.
10. A dynamic random access memory (DRAM), comprising:
a receiver and decoder circuit configured to receive a plurality of multilevel signals corresponding to a plurality of symbols and to decode the plurality of multilevel signals to recover a plurality of bits, wherein a count of the
plurality of bits is greater than a
count of the plurality of symbols,
the receiver and decoder circuit configured to use a pair of reference voltages to determine signal levels of each of the plurality of multilevel signals and to decode the plurality of multilevel signals based on the determined multilevel signal levels, and wherein the receiver and decoder circuit includes a plurality of pairs comparators
associated with the plurality of multilevel signals, respectively, a first pair of the plurality of pairs of comparators is configured to input a first multilevel signal of the plurality of multilevel signals and to input the pair of reference voltages, and a second pair of the plurality of pairs of comparators is configured to input a second multilevel signal of the plurality of multilevel signals and to input the pair of reference voltages, and wherein only two reference voltages including the pair of reference voltages are used to determine signal levels of each of the plurality of multilevel signals.
19. A method, comprising: converting, by a multilevel signal encoder
including a plurality of logic circuits each configured to input a plurality of bitstreams, the plurality of bitstreams into a plurality of multilevel signals
at a first device, wherein a count of the plurality of bitstreams is greater than a count of the multilevel signals; and driving the plurality of multilevel signals onto respective signal lines of an I/O bus to a second device via individual drivers, wherein each of the plurality of multilevel signals is configured to be one of more than two signal levels, wherein driving the plurality of multilevel signals onto the respective signal lines comprises controlling each of a plurality of sections of a driver associated with one of the plurality of multilevel signals, and wherein first and second control signals are used to control respective sections of the plurality of sections of the driver
associated with one of the plurality of multilevel signals, and each of the first and second control signals is generated based on all of the plurality of bitstreams.
15. A method, comprising: converting, by a multilevel signal encoder
of a dynamic random access memory (DRAM)
including a plurality of logic circuits each configured to input a plurality of
into
a plurality of multilevel signals corresponding to a plurality of symbols
at a first device, wherein a count of the plurality of bits is greater than a
count of the symbols; and driving
the plurality of multilevel signals onto respective signal lines of an I/O bus to a second device via individual drivers, wherein each of the plurality of multilevel signals is configured to be one of more than two signal levels, wherein driving the plurality of multilevel signals onto the respective signal lines comprises controlling each of a plurality of sections of a driver associated with one of the plurality of multilevel signals, and wherein first and second control signals are used to control respective sections of the plurality of sections of the driver.
24. A method, comprising: determining, at a host, voltage levels of each of a
plurality of multilevel signals received from a memory; and
decoding the plurality of the multilevel signals based on the determined voltage levels to recover a plurality of bitstreams, wherein determining the voltage levels of each of the plurality of multilevel signals received from the memory includes comparing a voltage level of a first multilevel signal of the plurality of multilevel signals with a pair of reference voltages to provide a first pair of output signals, and further includes comparing a voltage level of a second multilevel signal of the plurality of multilevel signals with the pair of reference voltages to provide a second pair of output signals, and wherein only two reference voltages including the pair of reference voltages are used to determine signal levels of each of the plurality of multilevel signals.
18. A method, comprising: determining, at a decoder, voltage levels of each of a plurality of multilevel signals received
at a memory, wherein the plurality of multilevel signals correspond to a plurality of symbols; and
decoding the plurality of the multilevel signals based on the determined voltage levels to recover a plurality of bits, wherein determining the voltage levels of each of the plurality of multilevel signals received at the memory includes comparing a voltage of a first
multilevel signal of the plurality of multilevel signals with a pair of reference voltages to provide a first pair of output signals, and further includes comparing a voltage level of a second multilevel signal of the plurality of multilevel signals with the pair of reference voltages to provide a second pair of output signals, and wherein only two reference voltages including the pair of reference voltages are used to determine signal levels of each of the plurality of multilevel signals.
For brevity sake, dependent claims are omitted from the table above. However, claims 3 – 7, 11 – 14, 16, 17, 20, and 21 share corresponding limitations to claims 1 – 3, 5, 7, 13 – 16, 22 – 23, 27, and 28 of U.S. Patent No. 10,365,833.
Claim Objections
Applicant is advised that should claim 4 be found allowable, claim 5 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim 4 is objected to because of the following informalities: claim 4 states “the multilevel signal encoder is further configured to, during the symbol period, to set the first and second control signals.” One of the instances of ‘to’ should be removed. Appropriate correction is required.
Claims 10 – 14 are objected to because of the following informalities: claim 10 states “wherein the receiver and decoder circuit includes a plurality of pairs comparators associated with the plurality of multilevel signals.” The examiner recommends amending claim 10 to state “wherein the receiver and decoder circuit includes a plurality of pairs of comparators associated with the plurality of multilevel signals.” Claims 11 – 14 inherit this objection based on their dependencies. Appropriate correction is required.
Claims 15 – 17 are objected to because of the following informalities: claim 15 states “A method, comprising: converting, by a multilevel signal encoder of a dynamic random access memory (DRAM) including a plurality of logic circuits each configured to input a plurality of into a plurality of multilevel signals corresponding to a plurality of symbols at a first device, wherein a count of the plurality of bits is greater than a count of the symbols.” There appears to be a typo in this limitation. The examiner suggests amending claim 15 to state “A method, comprising: converting, by a multilevel signal encoder of a dynamic random access memory (DRAM) including a plurality of logic circuits each configured to input a plurality of bits, into a plurality of multilevel signals corresponding to a plurality of symbols at a first device, wherein a count of the plurality of bits is greater than a count of the symbols,” or the like. Claims 16 – 17 inherit this objection based on their dependencies. Appropriate correction is required.
Claims 27 – 34 are objected to because of the following informalities: claim 27 states “a plurality of driver circuits configured to transmit the plurality of symbols to the DRAM device, wherein individual drivers of the plurality of driver circuits is configured to drive more than two voltages.” The examiner recommends amending claim 27 to state “a plurality of driver circuits configured to transmit the plurality of symbols to the DRAM device, wherein individual drivers of the plurality of driver circuits are configured to drive more than two voltages” or “a plurality of driver circuits configured to transmit the plurality of symbols to the DRAM device, wherein each individual driver of the plurality of driver circuits is configured to drive more than two voltages.” Claims 28 – 34 inherit this objection based on their dependencies. Appropriate correction is required.
Claim 29 is objected to because of the following informalities: claim 29 states “wherein a first plurality of the plurality of output signals are based on a comparison of the voltage to the first reference voltage an a second plurality of the plurality of the plurality of output signals are based on a comparison of the voltage to the second reference voltage.” The examiner recommends amending claim 29 to state “wherein a first plurality of the plurality of output signals are based on a comparison of the voltage to the first reference voltage and a second plurality of the plurality of the plurality of output signals are based on a comparison of the voltage to the second reference voltage.”
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22 – 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Jalalifar et al., ‘An Energy-Efficient Mobile PAM Memory Interface for Future 3D Stacked Mobile DRAMs’ (hereinafter referred to as Jalalifar) in view of Farzan et al., ‘A LOW-COMPLEXITY POWER-EFFICIENT SIGNALING SCHEME FOR CHIP-TO-CHIP COMMUNICATION’ (hereinafter referred to as Farzan) (from Applicant’s IDS).
Referring to claim 22, Jalalifar discloses “A memory controller” (Figure 2 controller) “comprising: a driver circuit comprising: a plurality of logic circuits configured to convert a plurality of bits into a plurality of symbols, wherein a number of the plurality of bits is greater than a number of the plurality of symbols” (section 2.2 and Figure 3 the transmitter includes an output driver, leakage suppression control logic, impedance control logic. D1 and D2 bits are encoded into symbols); a driver “configured to drive the plurality of symbols onto a” “signal line[s] to provide the plurality of symbols to a memory device, wherein” the driver is “configured to drive more than two voltages” (Figures 2 and 3 controller drives symbols of multiple voltages to DRAM receivers); “and an interface circuit including the driver circuit, the interface circuit configured to provide a first control signal and a second control signal to the memory device, wherein the first and second control signals are configured to control respective sections of a second driver circuit of the memory device” (Figures 2, 3, and 5 ODT signals are sent to multiple receiver drivers of the memory device, control logic sends signals to transmit drivers).
Jalalifar does not appear to explicitly disclose “and a plurality of drivers configured to drive the plurality of symbols onto a plurality of signal lines to provide the plurality of symbols to a memory device” wherein “individual ones of the plurality of drivers are configured to drive more than two voltages.”
However, multilevel signal driving over a plurality of signal lines is known in the art. For example, Farzan discloses “and a plurality of drivers configured to drive the plurality of symbols onto a plurality of signal lines to provide the plurality of symbols” wherein “individual ones of the plurality of drivers are configured to drive more than two voltages” (Figure 9(a) multiple 3-level PAM drivers outputting to Line1-4).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Farzan with Jalalifar so that the transmitter/receiver structure of Farzan is used to connect the controller and memory of Jalalifar and “to provide the plurality of symbols to a memory device.”
Jalalifar and Farzan are analogous art because they are from the same field of endeavor, which is multilevel encoding and signaling.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jalalifar and Farzan before him or her, to modify the teachings of Jalalifar to include the teachings of Farzan so that a plurality of drivers are configured to drive the plurality of symbols onto a plurality of signal lines to provide the plurality of symbols to a memory device.
The motivation for doing so would have been to provide a means for increasing throughput of the memory interface. In other words, the multiple channels of Farzan provides for higher throughput capability.
Therefore, it would have been obvious to combine Farzan with Jalalifar to obtain the invention as specified in the instant claim.
As per claim 23, Farzan discloses “the plurality of bits includes three bits, and the plurality of symbols includes two symbols corresponding to the three bits” (Fig. 9A three bitstreams b0-b2 are mapped to two multilevel signals Line1 and Line2 while three bitstreams b3-b5 are mapped to two multilevel signals Line3 and Line4).
As per claim 24, Jalalifar discloses “the plurality of bits includes two bits, and the plurality of symbols includes one symbol corresponding to the two bits” (Figure 3 D1 and D2 bits in to encoder and one symbol out from encoder).
As per claim 26, Jalalifar discloses “the driver circuit is configured to map the plurality of bits to a combination of voltages corresponding to the plurality of symbols using a pulse amplitude modulation architecture” (Figure 3 PAM transmitter mapping bits to multilevel symbols using a Pulse Amplitude Modulation architecture).
Claims 27 – 30, 33, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Jalalifar in view of Farzan, as applied to claims above, further in view of Shirani, U.S. Patent Application 20050122143 (hereinafter referred to as Shirani) (from Applicant’s IDS).
Referring to claim 27, Jalalifar discloses “A system comprising: a dynamic random access memory (DRAM) device configured to transmit and receive a plurality of symbols, wherein each of the plurality of symbols corresponds to two or more bits and each of the plurality of symbols is represented by a different voltage of a plurality of voltages” (Figure 2 DRAM with Tx and Rx connects to CPU controller. Figure 3 PAM transmitter with D1 and D2 bits and multilevel symbol output); “a memory controller configured to transmit and receive the plurality of symbols” (Figure 2 controller), “the memory controller comprising: a circuit configured to convert a plurality of bits into a plurality of symbols” (Figures 2 and 3 controller with Tx and transmitter design showing D1 and D2 bits converted into multilevel symbol output); “and a” “driver circuit[s] configured to transmit the plurality of symbols to the DRAM device, wherein” the “driver[s]” “is configured to drive more than two voltages” (Figures 2 and 3 controller drives symbols of multiple voltages to DRAM receivers); “and wherein the DRAM device is configured to receive the plurality of symbols from the memory controller from the I/O bus and convert the plurality of symbols into a plurality of bits, and store the plurality of bits in a memory array” (Figures 2 and 3 DRAM with Rx receiving the multilevel symbols from the controller. Figure 5 receiver design shows converting the received multilevel symbols into a plurality of bits D1 and D2. Figure 2 ‘input data to memory’ and first paragraph under Figure 4 describes write command).
Jalalifar does not appear to explicitly disclose “and a plurality of driver circuits configured to transmit the plurality of symbols to the DRAM device” wherein “individual drivers of the plurality of driver circuits [are] configured to drive more than two voltages” and “an I/O bus comprising a plurality of channels coupled between the DRAM device and the memory controller, wherein the plurality of symbols are transmitted on the plurality of channels, wherein a number of the plurality of channels is less than a number of bits represented by the plurality of symbols transmitted.”
However, multilevel signal driving over a plurality of signal lines is known in the art. For example, Farzan discloses “and a plurality of driver circuits configured to transmit the plurality of symbols” wherein “individual drivers of the plurality of driver circuits [are] configured to drive more than two voltages” (Figure 9(a) multiple 3-level PAM drivers outputting to Line1-4) and “an I/O bus comprising a plurality of channels coupled between the” devices, “wherein the plurality of symbols are transmitted on the plurality of channels, wherein a number of the plurality of channels is less than a number of bits represented by the plurality of symbols transmitted” (Figures 7 – 9 receiver and transmitter with multiple lines, each line being the output of a 3-level PAM driver)
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Farzan with Jalalifar so that the transmitter/receiver structure of Farzan is used to connect the controller and memory of Jalalifar and to transmit the plurality of symbols to the DRAM device.
Jalalifar and Farzan are analogous art because they are from the same field of endeavor, which is multilevel encoding and signaling.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jalalifar and Farzan before him or her, to modify the teachings of Jalalifar to include the teachings of Farzan so that a plurality of drivers are configured to drive the plurality of symbols onto a plurality of signal lines to provide the plurality of symbols to a memory device.
The motivation for doing so would have been to provide a means for increasing throughput of the memory interface. In other words, the multiple channels of Farzan provides for higher throughput capability.
Neither Jalalifar nor Farzan appears to explicitly disclose “the plurality of driver circuits have a same impedance.”
However, Jalalifar describes avoiding impedance mismatch (section 2.2 on page 3). Also, as above, Farzan has four drivers, each driving a multilevel signal (Figure 9(a)). Further, Shirani discloses that line drivers typically must satisfy two requirements: first generate a certain voltage swing across the transmission line, and second have an output impedance that is matched to the line characteristic impedance to absorb signals arriving at the transmitter and avoid reflections back to the line ([0002]).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to utilize drivers with the same impedance in order to match the line characteristic impedance of each specific line.
Jalalifar, Farzan, and Shirani are analogous art because they are from the same field of endeavor, which is multilevel encoding and signaling.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jalalifar, Farzan, and Shirani before him or her, to modify the teachings of Jalalifar and Farzan to include the teachings of Shirani so that the plurality of driver circuits have a same impedance.
The motivation for doing so would have been to absorb signals arriving at the transmitter and avoid reflections back to the line (as stated by Shirani at [0002]). The lines may be of the same impedances and/or lengths based on the design of the circuitry, layout of a printed circuit board, etc.
Therefore, it would have been obvious to combine Shirani with Jalalifar and Farzan to obtain the invention as specified in the instant claim.
As per claim 28, Jalalifar discloses “the memory controller further comprises a receiver circuit comprising a plurality of comparators configured to provide a plurality of output signals based on a comparison of a voltage corresponding to a symbol of the plurality of symbols to a first reference voltage and a second reference voltage” (Figure 5 PAM receiver design including comparators comparing VREF1, VREF2 and outputting signals based on the comparisons).
As per claim 29, Jalalifar discloses “a first plurality of the plurality of output signals are based on a comparison of the voltage to the first reference voltage [and] a second plurality of the plurality of the plurality of output signals are based on a comparison of the voltage to the second reference voltage” (Figure 5 PAM receiver design including comparators comparing VREF1, VREF2 and outputting signals based on the comparisons).
As per claim 30, Jalalifar discloses “the memory controller further comprises a decoder circuit configured to provide the two or more bits corresponding to the symbol based on the plurality of output signals” (Figure 5 PAM receiver design including comparators comparing VREF1, VREF2 and outputting signals based on the comparisons. A decoder receives the signals and provides D1 and D2 corresponding to the received symbol).
As per claim 33, Jalalifar discloses “the plurality of symbols are transmitted using pulse amplitude modulation” (Figure 3 PAM transmitter and Figure 5 PAM receiver).
As per claim 34, Jalalifar discloses “a number of the plurality of voltages is” four (Figure 3 PAM transmitter and Figure 5 PAM receiver show four voltages for the multilevel data. Abstract describes 4-PAM).
However, Farzan discloses another multilevel signaling method wherein “a number of the plurality of voltages is three” (Figure 9 3-level PAM driver).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to try utilizing Farzan’s 3-level PAM in the system of Jalalifar.
The motivation for doing so would have been to find an ideal number of voltages for the multilevel signal. It is understood that different PAM levels have different complexities, data rates, and noise issues. It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to try to find a best fit for the system.
Allowable Subject Matter
Claims 2 – 21 contain allowable subject matter.
The following is an examiner’s statement of reasons for allowable subject matter: The primary reason for the indication of allowable subject matter of the claims in this application is the inclusion of the specific details of a driver circuit including a multilevel signal encoder including a plurality of logic circuits, the driver is a multi-leg driver for the multilevel signals, wherein each of the sections of the driver circuit is associated with one of the plurality of symbols, wherein first and second control lines control respective sections of the driver circuit, as are now included in independent claim 2, in combination with the other elements recited, which is not found in the prior art of record.
The primary reason for the indication of allowable subject matter of the claims in this application is the inclusion of the specific details of the receiving a plurality of multilevel signals corresponding to a plurality of symbols, decoding the multilevel signals using a pair of reference voltages, the plurality of pairs of comparators with respective plurality of multilevel signals, the specific signals input to each pair of comparators, and only two reference voltages being used, as are now included in independent claims 10 and 18, in combination with the other elements recited, which is not found in the prior art of record.
The primary reason for the indication of allowable subject matter of the claims in this application is the inclusion of the specific details of converting, by a multilevel signal encoder of a dynamic random access memory (DRAM) including a plurality of logic circuits each configured to input a plurality of [bits], into a plurality of multilevel signals corresponding to a plurality of symbols at a first device, individual drivers used to drive the multilevel signals onto respective signal lines, and controlling respective sections of a driver using first and second control lines, as are now included in independent claim 15, in combination with the other elements recited, which is not found in the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 8, 9, 19, 25, 31, and 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 11621038 teaches channels between a host and a memory device, using pulse amplitude modulation and drivers.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184