DETAILED ACTION
This Office Action is in response to the communication filed on 4/14/2026.
Claims 1-20 are pending.
Claims 1, 8 and 15 have been amended.
Claims 1-20 are rejected.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/29/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20, Page 8 of Remarks filed 4/14/2026, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specifically, applicant is arguing that “executing as hardware circuitry” is not explicitly taught by Vlad in view of Yoshino and in further view of Dalli. Examiner disagrees. Yoshino broadly teaches implement processed in hardware and Dalli more explicitly teaches implementing Boolean logic (decision trees) directly as a hardware circuit. Applicant defines “A decision tree is essentially a Boolean function” at paragraph 0040.
Further, applicant asserts that the “Office Action acknowledges that the prior art is deficient but is arguing that claim language is broad enough that it encompasses conventional software-based encrypted decision trees running on any general-purpose hardware”. Examiner disagrees with this characterization. If “claim language is broad enough that it encompasses conventional software-based encrypted decision trees running on any general-purpose hardware” and the prior art reads on “conventional software-based encrypted decision trees running on any general-purpose hardware” then the prior art is not deficient.
Dependent claims are also rejected for inheriting the deficiencies of the independent claims set forth above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over by Vald (U.S. 20200382273), in view of Yoshino (U.S. 20190318104) and in further view of Dalli (U.S. 20220398460)
Regarding claims 1, 8 and 15,
Vald discloses: A method, comprising:
initiating, by a server system comprising a host device, an the (Vald [0003, 0017-0020, 0024, 0032, 0065-0067] teaches the user (client) device [0003, 0022-0032, 0044-0051] teaches obtaining encrypted data from a client device, which is encrypted by using FHE, and processing it using a machine learning model (which can be a tree-based model) which perform operations on the encrypted data to make an encrypted prediction which is then sent back to the client device [0064-0065] teaches that the method can be implemented using various accelerators)
receiving, by the host device, an input, from the user device, to be evaluated using the (Vald [0003,0017, 0022-0032, 0044-0051, 0065-0067] teaches the machine learning device obtains encrypted data, wherein the encrypted data is encrypted using fully homomorphic encryption, which is the agreed upon encryption schema)
evaluating, by the hardware circuitry of the accelerator implementing the ; (Vald [Abstract, 0003, 0017, 0022-0032, 0044-0051, 0065-0067] teaches that the machine learning device performs at least one computation on the encrypted data while the encrypted data remains encrypted)
generating, by the hardware circuitry of the accelerator implementing the (Vald [0003, 0017, 0022-0032, 0044-0051, 0065-0067] teaches “One example method generally includes obtaining, at a computing device, encrypted data, wherein the encrypted data is encrypted using fully homomorphic encryption and performing at least one computation on the encrypted data while the encrypted data remains encrypted”; [0064-0065] teaches using an FPGA accelerator)
Vlad does not explicitly disclose: encrypted decision tree;
wherein the hardware circuitry comprises logic circuits with encrypted threshold values embedded therein, the logic circuits physically implement encrypted threshold comparisons at internal nodes of the encrypted decision tree model;
wherein the hardware circuitry implements encrypted comparison operations at internal nodes of the encrypted decision tree model, the encrypted comparison operations using the logic circuits comparing the encrypted threshold values with encrypted input values…
the logic circuits physically implement (Boolean operations) at internal nodes;
evaluating… using the logic circuits with the embedded encrypted threshold values
However, in the same field of endeavor Yoshino teaches:
encrypted decision tree; ; comparing the encrypted threshold values with encrypted input values; evaluating… (Yoshino [0035-0038] teaches comparable encryption (In the embodiments, the encrypted data is represented by E( )); [0039-0042, 0053-0059, 0065, 0078-0089, 0105-0111] teaches an encrypted determination module which can perform learning (generate a decision tree) while keeping the learning and analysis secret (operations are performed at nodes of the tree and the tree along with the data remains encrypted; [Fig. 12A, Fig. 16A] shows examples of encrypted decision trees, and decision tree models, which use threshold values, which are encrypted, to make determinations and comparisons to produce an encrypted output corresponding to an encrypted input)
Vlad and Yoshino are analogous art because they are from the same field of endeavor secure tree based learning.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Vlad and Vlad before him or her, to modify the method of Vlad to include the encrypted comparisons using encrypted decision trees of Yoshino because it will improve data secrecy at learning and analysis phases of decision tree analysis.
The motivation for doing so would be [“there is a possibility that data for learning contains sensitive information, which requires secrecy of the data to be improved even in a learning phase of a decision tree analysis. Therefore, one embodiment of this invention has an object to improve secrecy of data in a learning phase of a decision tree analysis.”] (Paragraph 0005-0006, 0070 by Yoshino)].
Therefore, it would have been obvious to combine Vlad and Yoshino to obtain the invention as specified in the instant claim.
While Yoshino teaches implementing by hardware but Vlad in view of Yoshino does not explicitly teach wherein the hardware circuitry comprises logic circuits… embedded therein, the logic circuits physically implement… at internal nodes
wherein the hardware circuitry implements… operations at internal nodes… using the logic circuits…;
the logic circuits physically implement (Boolean operations) at internal nodes;
evaluating… using the logic circuits with the embedded…
However, in the same field of endeavor Dalli teaches wherein the hardware circuitry comprises logic circuits… embedded therein, the logic circuits physically implement… at internal nodes; wherein the hardware circuitry implements… operations at internal nodes… using the logic circuits…; the logic circuits physically implement (Boolean operations) at internal nodes; evaluating… using the logic circuits with the embedded… (Dalli [Fig. 1, 0054-0062, 0066-0068, 0148-0149, 0188, 0219-0221, 0288, 0420] teaches INNs/XNNs as “static hardcoded circuit when implemented in hardware” for the including of Boolean logic and decision trees consisting of a number of nodes and edges, and other events, triggers, constraints, and actions, for example, [0219] recites “representation format may include… IF-THEN-ELSE style rules… Boolean logic. The representation format can also be implemented directly as a hardware circuit, which may be implemented either using flexible architectures like FPGAs or more static architectures like ASICs or analog/digital electronics”; [0288] directly converted into a hardware system)
Vlad in view of Yoshino and Dalli are analogous art because they are from the same field of endeavor secure multi-party computing including logic processing and homomorphic encryption.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Vlad in view of Yoshino and Dalli before him or her, to modify the method of Vlad in view of Yoshino to include the hardware architecture of Dalli because hardcoding the secure/encrypted (homomorphic) processing into circuitry will result in it will have improved performance.
The motivation for doing so would be [“Exemplary hardware implementations may offer better power consumption, higher throughputs and miniaturization while opening up edge applications and IoT deployments, but may be, in some cases, less flexible than software implementations”] (Paragraph 0045, 0407-0414 by Dalli)].
Therefore, it would have been obvious to combine Vlad in view of Yoshino and Dalli to obtain the invention as specified in the instant claim.
Similar Claim 8 additionally discloses: A non-transitory computer readable medium comprising one or more sequences of instructions, which, when executed by one or more processors, causes a server system to perform operations comprising: (Vald [0013, 0064-0065] teaches non-transitory computer readable medium)
Similar Claim 15 additionally discloses: A system, comprising: (Vald [0013 and 0019] teaches the functions of computing environment 100 may be performed by… a computing system)
Regarding claims 2 and 9,
Vald in view of Yoshino discloses: The method of claim 1, wherein the host device is one of a server, a cluster of servers, a cloud computing service, or an edge computing device, and (Vald [0003-0019, 0022-0032, 0044-0051] teaches that the host device can be cloud computing servers/services)
wherein the accelerator is one of a field programmable gate array, graphics processing unit, or tensor processing unit. (Vald [0064-0065] teaches FPGA accelerator)
Regarding claims 3, 10 and 16,
Vald in view of Yoshino discloses: The method of claim 1, wherein the agreed upon encryption schema is a fully homomorphic encryption algorithm. (Vald [0003, 0022-0032, 0044-0051] teaches
Regarding claims 4, 11 and 17,
Vald in view of Yoshino discloses: The method of claim 3, wherein the (Vald [0003-0018, 0022-0032, 0044-0051] a tree-based machine learning model and encryption using public/private key pairs)
Vlad does not explicitly disclose: encrypted decision tree
However, in the same field of endeavor Yoshino discloses: encrypted decision tree (Yoshino [0035-003-0042, 0053-0059, 0065, 0078-0089, 0105-0111] teaches encrypted decision tree models (In the embodiments, the encrypted data is represented by E( )); [Fig. 12A, Fig. 16A] shows examples of encrypted decision trees)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Yoshino for similar reasons as cited in claim 1.
Regarding claims 5, 12 and 18,
Vald in view of Yoshino discloses: The method of claim 1, wherein the agreed upon encryption schema is an order-preserving cryptography schema. (Vald [0003-0019, 0022] teaches order preserving encryption schemes being used)
Regarding claims 6, 13 and 19,
Vald in view of Yoshino discloses: The method of claim 5, wherein the (Vald [0003-0032, 0044-0051] teaches a tree-based machine learning model and a key management service which uses the same keys thought the operations)
Vlad does not explicitly disclose: encrypted decision tree
However, in the same field of endeavor Yoshino discloses: encrypted decision tree (Yoshino [0035-003-0042, 0053-0059, 0065, 0078-0089, 0105-0111] teaches encrypted decision tree models (In the embodiments, the encrypted data is represented by E( )); [Fig. 12A, Fig. 16A] shows examples of encrypted decision trees)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Yoshino for similar reasons as cited in claim 1.
Regarding claims 7, 14 and 20,
Vald in view of Yoshino discloses: The method of claim 1, further comprising:
Vald does not explicitly disclose: generating, by the server system, the encrypted decision tree model by encrypting computations performed at each internal node of the encrypted decision tree model;
extracting, by the server system, decision rules performed from a root node of the encrypted decision tree model to each leaf node; and
converting, by the server system, the decision rules into source code for upload to the accelerator.
However, in the same field of endeavor Yoshino discloses: generating, by the server system, the encrypted decision tree model by encrypting computations performed at each internal node of the encrypted decision tree model; (Yoshino [0035-003-0042, 0053-0059, 0065, 0078-0089, 0105-0111] teaches encrypted decision tree models (In the embodiments, the encrypted data is represented by E( )); [Fig. 12A, Fig. 16A] shows examples of encrypted decision trees)
(Yoshino [0006, 0091-0101] teaches identification and extraction of branching rules)
Vald in view of Yoshino does not explicitly disclose: extracting, and converting, by the server system, the decision rules into source code for upload to the accelerator.
However, in the same field of endeavor Dalli teaches: extracting, and converting, by the server system, the decision rules into source code for upload to the accelerator. Dalli [0188, 0219, 0275] teaches model interpretability which includes generalized rule-based format of decision trees; [0288] In an exemplary embodiment, AutoXAI model search evolution utilizing neuro-symbolic methods may be used to generate source code in a suitable formal programming language that is intended to be interpreted or compiled and then subsequently executed on appropriate hardware, or directly converted into a hardware system.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Dalli for similar reasons as cited in claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure.
Kreinin 6/9/2016 (US 20170103022) teaches that a generated decision trees can be converted into programming code.
Gentry 6/18/2019 (US 20200403781) teaches: using homomorphic encryption at the bit level.
Verma 10/19/2018 (US 20200125739) teaches: Distributed machine learning employs a central fusion server that coordinates the distributed learning process. Preferably, each of set of learning agents that are typically distributed from one another initially obtains initial parameters for a model from the fusion server. Each agent trains using a dataset local to the agent. The parameters that result from this local training (for a current iteration) are then passed back to the fusion server in a secure manner, and a partial homomorphic encryption scheme is then applied. In particular, the fusion server fuses the parameters from all the agents, and it then shares the results with the agents for a next iteration. In this approach, the model parameters are secured using the encryption scheme, thereby protecting the privacy of the training data, even from the fusion server itself.
Aggarwal 8/8/2023 (US 20240054353) teaches: According to an aspect, there is provided an apparatus comprising means for receiving, from a server, an authorization request for a federated learning operation, the authorization request identifying a plurality of user equipment, and means for determining, using subscription data associated with each of the plurality of user equipment, whether each of the plurality of user equipment are authorized to be used by the server for the federated learning operation. The apparatus also comprising means for, in response to determining that at least two of the plurality of user equipment are authorized, providing a message to each of the at least two of the plurality of user equipment that are authorized, each message comprising an encryption key associated with the federated learning operation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS A CARNES whose telephone number is (571)272-4378. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shewaye Gelagay can be reached at (571) 272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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THOMAS A. CARNES
Examiner
Art Unit 2436
/THOMAS A CARNES/Examiner, Art Unit 2436
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