Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
DETAILED ACTION
Claims 1-20 are presented for examination.
This is a first action on the merits based on Applicant’s claims submitted 11/24/2025.
In an amendment filed on 11/24/2025, the Applicant amended claims 1 and 11. Therefore, claims 1-20 are pending for examination.
Response to Arguments
Regarding rejection under 35 USC § 102, the arguments filed 11/24/2025 have been considered but are moot in view of new grounds of rejection. See rejection section below.
SPECIFICATION
The specification filed on 10/03/2023 has been reviewed and accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-20 rejected under 35 U.S.C. 103 as being unpatentable over *Aerabi et al. (NPL: Mystic: Mystifying IP cores Using an Always-On FSM Obfuscation Model, hereinafter “Mystic”) in view of Slusarczyk, A. S. (NPL: Decomposition and encoding of finite state machines for FPGA implementation, hereinafter “Slusarczyk”).
*Provided by Applicant’s IDS
Regarding claim 1, Mystic teaches:
1. A method of state permutation logic locking (SPeLL) for sequential circuits, the method comprising:
encrypting original states of a finite state machine (FSM) to produce encrypted states (Fig. 3, FSM encoding, masking techniques, page 629, Section IV “a masking technique” ), by [modifying state bit encodings within the FSM to] transition an initial order of the original states (page 629, line 21, Section IV “original FSM” ) into a secret permutation of the encrypted states (masking techniques utilizing a key, page 629, line 21, Section IV “iterative masking algorithm to systematically add obfuscation transitions or states…To choose an appropriate state, we propose a simple but effective Security Metric that can be assigned to each state s…”;), wherein the secret permutation is different than the initial order (page 629, section IV, i.e. original FSM vs. addition of states based on key input to add more state transitions and/or additional states to mask the original FSM), and maintains a number of original states and a number of state transitions of the FSM corresponding to the original states (fig. 1, page 631 Section V. Mystic Hardware Overheads, Section B. ASIC Implementation Results, left column, lines 8-11 “The Mystic method does not add any additional state to the FSM. Instead it adds extra combinational logic to produce the transition guard considering the key inputs.”);
determining a cryptographic key that corresponds to the transition from the initial order of the original states to the secret permutation of the encrypted states (page 629, Section IV, “The key underpinning of the proposed technique is the concept that a designer may add more state transitions and/or additional states to mask the original FSM…. Locking transitions are added to the original circuit’s FSM in a manner that allows the circuits to check their activation keys at runtime.”); and
decrypting the encrypted states, by using the cryptographic key by [modifying the state bit encodings to] transition from the secret permutation of the encrypted states back to the initial order of the original states (page 630 “each state is obfuscated using a subset of the masking key. All of the key bits in that subset should be correct for the FSM to perform a single transition correctly”).
Mystic does not explicitly teach yet Slusarczyk suggests:
Modifying state bit encodings to make transitions (Slusarczyk: figure 2.3, page 28, i.e. modification of the FSM yields a modified FSM which behavior of the modified FSM does not change from the original machine – Examiner notes that this modification implies a modification at the RTL level).
Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to have implemented a modification of the state bit encodings of the finite state machine, as taught by Slusarzyk, to Mystic’s invention. The motivation to do so would have been to apply effective state encoding by reassuring that the modification of the FSM still has the same behavior of the original state machine (Slusarczyk: Summary and page 28).
Regarding claim 2, the combination of Mystic and Slusarczyk teaches:
2. The method of claim 1, comprising: defining the encrypting of the original states of the sequential circuit at a Register-Transfer Level (RTL) (page 630, Section V “The tool takes the RTL description of a circuit, extracts the state machine and then obfuscates it using the key provided by the user.”).
Regarding claim 3, the combination of Mystic and Slusarczyk teaches:
3. The method of claim 1, comprising: encrypting the original states of the sequential circuit to produce the secret permutation of the encrypted states having a number of encrypted states equal to a number of the original states (Mystic: Fig. 1 of Background section (page 627) teaches an equal number of obfuscated states are added to the FSM of the original design).
Regarding claim 4, the combination of Mystic and Slusarczyk teaches:
4. The method of claim 1, comprising: encrypting all of the original states to produce the encrypted states (Mystic: page 630 “each state is obfuscated using a subset of the masking key. All of the key bits in that subset should be correct for the FSM to perform a single transition correctly”).
Regarding claim 5, the combination of Mystic and Slusarczyk teaches:
5. The method of claim 1, comprising: encrypting a subset of the original states to produce the encrypted states (Mystic: page 630 left column lines 12-14: “Therefore the first bits of the key are negated and inserted as obfuscating transition of state S1 in Figure 4-B and state S4 in Figure 4-C.”).
Regarding claim 6, the combination of Mystic and Slusarczyk teaches:
6. The method of claim 1, comprising: encrypting the original states of the sequential circuit by encrypting selected bits representing the original states (Mystic: page 630 left column lines 12-14: “Therefore the first bits of the key are negated and inserted as obfuscating transition of state S1 in Figure 4-B and state S4 in Figure 4-C.”).
Regarding claim 7, the combination of Mystic and Slusarczyk teaches:
7. The method of claim 1, comprising: determining the cryptographic key by receiving the cryptographic key from an external device external to the sequential circuit (Mystic: page 626, Introduction Section, “Using the MUX primitive as key-gates instead of XOR/XNOR has been proposed in [6] and [5]. When supplied key-inputs are correct, the MUXs pass the correct input”).
Regarding claim 8, the combination of Mystic and Slusarczyk teaches:
8. The method of claim 7, wherein the external device is a tamper-proof key provider residing in an embedded system with the sequential circuit (Mystic: page 626, Introduction section, “When supplied key-inputs are correct, the MUXs pass the correct input, otherwise they pass a wrong value coming from other parts of the circuit. Overall, the goal in [5] is to achieve a high HD between the correct and wrong keys.”; Examiner notes it’s known in the art that a higher hamming distance is an indicator used as metric to detect tampering attempts by identifying data that has been altered, thereby indicating a tampering event).
Regarding claim 9, the combination of Mystic and Slusarczyk teaches:
9. The method of claim 7, wherein the external device is communicatively coupled to an embedded system in which the sequential circuit resides (Mystic: page 626, Introduction section, “When supplied key-inputs are correct, the MUXs pass the correct input, otherwise they pass a wrong value coming from other parts of the circuit. Overall, the goal in [5] is to achieve a high HD between the correct and wrong keys.”; Examiner notes that such circuits imply a coupling).
Regarding claim 10, the combination of Mystic and Slusarczyk teaches:
10. The method of claim 1, wherein the sequential circuit resides on an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a programmable logic controller (PLC) (Mystic: page 630, Table II and Section A, i.e. implementation in FPGA).
Regarding claim 11, the claims are set forth and rejected as it has been discussed in claim 1.
Regarding claim 12, the claims are set forth and rejected as it has been discussed in claim 2.
Regarding claim 13, the claims are set forth and rejected as it has been discussed in claim 3.
Regarding claim 14, the claims are set forth and rejected as it has been discussed in claim 4.
Regarding claim 15, the claims are set forth and rejected as it has been discussed in claim 5.
Regarding claim 16, the claims are set forth and rejected as it has been discussed in claim 6.
Regarding claim 17, the claims are set forth and rejected as it has been discussed in claim 7.
Regarding claim 18, the claims are set forth and rejected as it has been discussed in claim 8.
Regarding claim 19, the claims are set forth and rejected as it has been discussed in claim 9.
Regarding claim 20, the claims are set forth and rejected as it has been discussed in claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
(1) US 2022/0284132 A1 teaches a method for securing logic circuits.
(2) US 2021/0192018 A1 teaches hardware intellectual property protection through provably secure state-space obfuscation.
(3) US 8,402,401 B2 teaches method for protecting an integrated circuit chip design.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIZBETH TORRES-DIAZ whose telephone number is (571)272-1787. The examiner can normally be reached on 9:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Linglan Edwards, can be reached on (571)270-5440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LIZBETH TORRES-DIAZ/Primary Examiner, Art Unit 2408
/January 8, 2026/
/ltd/