DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 6, 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al., US 2012/0258575 (corresponding to US 9,960,278), in view of Yamazaki et al., US 2017/0236844 (corresponding to US 10,115,742).
In re Claim 1, Sato discloses a semiconductor device (Fig. 1B) comprising: an oxide insulating layer 102; an oxide semiconductor layer 106 above the oxide insulating layer 102; a gate electrode 112 above the oxide semiconductor layer 106; a gate insulating layer 110 between the oxide semiconductor layer 106 and the gate electrode 112; and a first insulating layer 114 covering the oxide semiconductor layer 106 and the gate electrode 112 (Figs. 1- 9; [0040 – 0294]).
Sato does not indicate that wherein the semiconductor device is divided into a first region overlapping the gate electrode, a second region not overlapping the gate electrode and overlapping the oxide semiconductor layer, and a third region not overlapping the gate electrode and the oxide semiconductor layer, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.
Yamazaki teaches a semiconductor device (Figs. 4) comprising: an oxide semiconductor layer 108; a gate electrode 112 above the oxide semiconductor layer 108; a gate insulating layer 110 between the oxide semiconductor layer 108 and the gate electrode 112; and a first insulating layer 116 covering the oxide semiconductor layer 108 and the gate electrode 112, wherein the semiconductor device (Fig. 4B) is divided into a first region 1R (Fig. A) overlapping the gate electrode 112, a second region 2R not overlapping the gate electrode 112 and overlapping the oxide semiconductor layer 108, and a third region 3R not overlapping the gate electrode 112 and the oxide semiconductor layer 108, the gate electrode 112 contacts the first insulating layer 116 in the first region 1R, the oxide semiconductor layer 108 contacts the first insulating layer 116 in the second region 2R, an amount of impurities contained in the oxide semiconductor layer 108 in the second region 2R ([0142]) is greater than an amount of impurities contained in the oxide semiconductor layer 108 in the first region 1R, and an amount of impurities contained in the oxide insulating layer 108 ([0143]) in the third region 3R is greater than an amount of impurities contained in the oxide insulating layer 108 in the second region 2R (Figs. 4, [0138 -0155).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine teachings of Sato and Yamazaki, and to use the specified structure for achieving high field-effect mobility as taught by Yamazaki ([0006]).
PNG
media_image1.png
200
400
media_image1.png
Greyscale
Fig. A. Yamazaki’s Fig. 4B annotated to show the details cited
However, Sato taken with Yamazaki does not specify that a thickness of the gate insulating layer 110 in the first region 1R is 200 nm or more.
It is known in the art that the thickness of the gate insulation layer is a result effective variable – because its mass depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the thickness of the gate insulating layer 110 in the first region 1R is 200 nm or more, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 2, Sato taken with Yamazaki discloses the semiconductor device according to Claim 1, wherein the first insulating layer 102 is nitride (Sato: [0046]).
In re Claim 6, Sato taken with Yamazaki discloses the Sato taken with Yamazaki discloses the semiconductor device according to Claim 1 further comprising: a second insulating layer 118 above the first insulating layer 116 (Yamazaki: Fig. 4B).
However, Sato taken with Yamazaki does not specify that the first insulating layer 116 is oxide, and the second insulating layer 118 is nitride.
Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the first insulating layer with oxide, and the second insulating layer with nitride., since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
In re Claim 14, Sato taken with Yamazaki discloses the semiconductor device according to Claim 1 wherein the first insulating layer 116 contacts the oxide insulating layer 102 (a top of Yamazaki’s substrate 102 being substituted with Sato’s substrate comprising substrate 100 and oxide insulating layer 102, Sato: Fig. 1B) in the third region 3R (Fig. A).
In re Claim 15, Sato taken with Yamazaki discloses all limitations of Claim 6 except for that a thickness of the first insulating layer 116 (Fig. A) is less than 50 nm. It is known in the art that the thickness of the first insulating layer is a result effective variable – because its volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the thickness of the first insulating layer 116 (Fig. A) is less than 50 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 16, Sato taken with Yamazaki discloses all limitations of Claim 6 except for that a thickness of the first insulating layer 116 is less than 150 nm. It is known in the art that the thickness of the first insulating layer is a result effective variable – because its volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the thickness of the first insulating layer 116 is less than 50 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sato.
In re Claim 17, Sato discloses a method for manufacturing a semiconductor device comprising: forming a first oxide insulating layer 102; forming an oxide semiconductor layer 106 above the first oxide insulating layer 102; exposing the first oxide insulating layer 102 by forming a pattern of the oxide semiconductor layer 106 above the first oxide insulating layer 102; forming a gate insulating layer 110 above the oxide semiconductor layer 106; forming a gate electrode 112 above the gate insulating layer 110; exposing the oxide semiconductor layer 106 and the first oxide insulating layer 114 by forming a pattern of the gate insulating layer and the gate electrode above the oxide semiconductor layer 106; implanting an impurity into the exposed oxide semiconductor layer 106 (Fig. 3A) and the first oxide insulating layer 114; forming a second oxide insulating layer 116 above each of the first oxide insulating layer 114, the oxide semiconductor layer 106, and the gate electrode 112; implanting an impurity into the second oxide insulating layer 116 (Fig. 3A); and forming an insulating layer 116 above the second oxide insulating layer 114 (Figs. 1- 9; [0040 – 0294]).
Sato does not specify that the insulating layer 116 above the second oxide insulating layer 114 is nitride. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to substitute insulating layer 116 with nitride, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
In re Claim 18, Sato discloses a method for manufacturing a semiconductor device comprising: forming a first oxide insulating layer 102; forming an oxide semiconductor layer 106 above the first oxide insulating layer 102; exposing the first oxide insulating 102 layer by forming a pattern of the oxide semiconductor layer 106 above the first oxide insulating layer 102; forming a gate insulating layer 110 above the oxide semiconductor layer 106; forming a gate electrode 112 above the gate insulating layer 110; exposing the oxide semiconductor layer 106 and the first oxide insulating layer 102 by forming a pattern of the gate insulating layer 110 and the gate electrode 112 above the oxide semiconductor layer 106; forming a second oxide insulating layer 114 above each of the first oxide insulating layer 102, the oxide semiconductor layer 106, and the gate electrode 112; implanting an impurity (Fig. 3A) into the oxide semiconductor layer 106, the first oxide insulating layer 102, and the second oxide insulating layer 114; and forming a nitride insulating layer 116 above the second oxide insulating layer 114 (Figs. 1- 9; [0040 – 0294]).
Sato does not specify that the second oxide insulating layer 114 having a hydrogen content of 1 x 1021 cm-3 or less, as well as that the insulating layer 116 above the second oxide insulating layer 114 is a nitride insulating layer.
It is known in the art that the hydrogen content is a result effective variable – because a specific mass density depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the hydrogen content of 1 x 1021 cm-3 or less , since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) (MPEP2144.04).
Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to substitute insulating layer 116 with a nitride insulating layer, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
Allowable Subject Matter
Claims 3-5 and 7-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 3: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 3 as: “a peak of a profile of the impurity in a thickness direction of the oxide insulating layer and the first insulating layer exists in the oxide insulating layer in the third region”, in combination with limitations of Claim 1 on which it depends.
In re Claim 4: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 4 as: “a peak of a profile of the impurity in a thickness direction of the oxide insulating layer, the oxide semiconductor layer, and the first insulating layer exists in the oxide semiconductor layer in the second region”, in combination with limitations of Claim 1 on which it depends.
In re Claim 5: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 5 as: “a peak of a profile of the impurity in a thickness direction of the oxide insulating layer, the oxide semiconductor layer, and the first insulating layer exists in the oxide insulating layer or near an interface between the oxide insulating layer and the oxide semiconductor layer in the second region”, in combination with limitations of Claim 1 on which it depends.
In re Claim 7: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 7 as: “a peak of a profile of the impurity in a thickness direction of the oxide insulating layer, the first insulating layer, and the second insulating layer exists in the oxide semiconductor layer”, in combination with limitations of Claims 1 and 6 on which it depends.
In re Claim 8: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 8 as: “a peak of a profile of the impurity in a thickness direction of the gate electrode and the first insulating layer exists in the gate electrode”, in combination with limitations of Claims 1 and 6 on which it depends.
In re Claim 9: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 9 as: “a peak of a profile of the impurity in a thickness direction of the oxide insulating layer, the oxide semiconductor layer, the first insulating layer, and the second insulating layer exists in the oxide semiconductor layer”, in combination with limitations of Claims 1 and 6 on which it depends.
In re Claim 10: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 10 as: “a peak of a profile of the impurity in a thickness direction of the oxide insulating layer, the oxide semiconductor layer, the first insulating layer, and the second insulating layer exists in the first insulating layer or near an interface between the oxide semiconductor layer and the first insulating layer”, in combination with limitations of Claims 1 and 6 on which it depends.
In re Claim 11: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 11 as: “a profile of the impurity in a thickness direction of the oxide insulating layer, the first insulating layer, and the second insulating layer includes a first peak and a second peak, the first peak exists in the oxide insulating layer, and the second peak exists in the first insulating layer”, in combination with limitations of Claims 1 and 6 on which it depends.
In re Claim 12: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 12 as: “a profile of the impurity in a thickness direction of the gate electrode and the first insulating layer includes a third peak and a fourth peak, the third peak exists in the gate electrode, and the fourth peak exists in the first insulating layer”, in combination with limitations of Claims 1, 6, and 11 on which it depends.
In re Claim 13: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 13 as: “a profile of the impurity in a thickness direction of the oxide insulating layer, the oxide semiconductor layer, the first insulating layer, and the second insulating layer includes a fifth peak and a sixth peak, the fifth peak exists in the oxide semiconductor layer, and the sixth peak exists in the first insulating layer.”, in combination with limitations of Claims 1, 6, 11, and 12 on which it depends.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B. Green can be reached at 5712703075. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893