Prosecution Insights
Last updated: July 17, 2026
Application No. 18/480,233

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Oct 03, 2023
Priority
Apr 16, 2021 — JP 2021-069749 +1 more
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
669 granted / 931 resolved
+3.9% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
62 currently pending
Career history
1009
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
83.7%
+43.7% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of FIG. 1 and reads upon Claims 1 - 3, 10 - 15, and 17 in the reply filed on 04/08/2026 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 - 3, 10 - 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MATSUBARA et al. 20160307854. PNG media_image1.png 718 751 media_image1.png Greyscale PNG media_image2.png 321 475 media_image2.png Greyscale Regarding claim 1, figs. 15-16 of MATSUBARA discloses a semiconductor device comprising: a plurality of conductive members including a first die pad (as labeled by examiner above) and a second die pad (as labeled by examiner above); a first semiconductor element 111 mounted on the first die pad; a second semiconductor element 112 mounted on the second die pad; an insulating element 12 electrically connected to the first semiconductor element and the second semiconductor element and electrically insulating the first semiconductor element and the second semiconductor element from each other; a sealing resin 6 covering the first semiconductor element, the second semiconductor element, the insulating element and at least a portion of each of the plurality of conductive members; and a support member (as labeled by examiner above) on which the insulating element 12 is mounted, at least a portion of the support member being an insulating portion containing a resin (portion with 213 – par [0098] - a molten resin is injected to into a mold cavity to form the sealing resin 6, molten resin can flow through the through-holes 213), wherein the first die pad and the second die pad are spaced apart from each other in a first direction (Y in fig. 15) orthogonal to a thickness direction of the first semiconductor element, and the support member is supported by at least one of the first die pad, the second die pad and the sealing resin (see figs. 15-16). Regarding claim 2, figs. 15-16 of MATSUBARA discloses wherein the support member is in contact with at least one of the first die pad and the second die pad. Regarding claim 3, figs. 15-16 of MATSUBARA discloses wherein the support member is located between the first die pad and the second die pad in the first direction, and the support member is supported by the first die pad and the second die pad (the structure as a whole supports the support member and the first die pad and the second die pad being parts of the structure). Regarding claim 10, figs. 15-16 of MATSUBARA discloses wherein the plurality of conductive members include a plurality of first terminal exposed from a first side of the sealing resin in the first direction and a plurality of second terminals exposed from a second side of the sealing resin in the first direction, the first semiconductor element is electrically connected to the plurality of first terminals, and the second semiconductor element is electrically connected to the plurality of second terminals. Regarding claim 11, figs. 15-16 of MATSUBARA discloses wherein the plurality of first terminals are arranged side by side in a second direction (X) orthogonal to the thickness direction and the first direction, and the plurality of second terminals arranged side by side in the second direction. Regarding claim 12, figs. 15-16 of MATSUBARA discloses wherein the first die pad includes a first pad portion 512/51 on which the first semiconductor element is mounted and two first suspending-lead portions 511/51 connected to opposite ends of the first pad portion in the second direction, and the two first suspending-lead portions 511/51 are exposed from the first side of the sealing resin in the first direction. Regarding claim 13, figs. 15-16 of MATSUBARA discloses wherein the second die pad includes a second pad portion 522/52 on which the second semiconductor element is mounted and two second suspending-lead portions 521/52 connected to opposite ends of the second pad portion in the second direction, and the two second suspending-lead portions are exposed from the second side of the sealing resin in the first direction. Regarding claim 14, par [0006] of MATSUBARA discloses that the insulating element is of one of an interactive type (inductor-coupled insulating element transmits an electric signal through inductive coupling of two inductors (coils), rather than via electric connection. Specifically, one of the coils converts an electric signal into a magnetic field, and the other coil converts the magnetic field back into an electric signal. This achieves transmission of the electric signal without electric connection) or a capacitive type. Regarding claim 15, figs. 15-16 of MATSUBARA wherein the insulating element includes a first transmitting/receiving portion 712/71 electrically connected to the first semiconductor element, a second transmitting/receiving portion 713/71 electrically connected to the second semiconductor element, and a relay portion 12a transmitting a signal between the first transmitting/receiving portion and the second transmitting/receiving portion, and in the thickness direction, the relay portion is located closer to the support member than the first transmitting/receiving portion and the second transmitting/receiving portion. Regarding claim 17, figs. 15-16 of MATSUBARA discloses further comprising a bonding layer (a layer portion of 6) between the support member and the insulating element, wherein the bonding layer is electrically insulating. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 03, 2023
Application Filed
May 29, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.6%)
3y 3m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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