Prosecution Insights
Last updated: October 27, 2026
Application No. 18/480,932

MULTILAYER COIL ARRAY

Non-Final OA §DP
Filed
Oct 04, 2023
Priority
Dec 12, 2022 — JP 2022-198007
Examiner
HOSSAIN, KAZI S
Art Unit
2837
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
521 granted / 649 resolved
+12.3% vs TC avg
Strong +16% interview lift
Without
With
+15.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
18 currently pending
Career history
679
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
66.9%
+26.9% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
7.6%
-32.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 649 resolved cases

Office Action

§DP
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of copending Application No. 18479292 Although the claims at issue are not identical, they are not patentably distinct from each other because claims (1, 5), 11 and 18-19 of copending Application No. 18479192 contains all the limitations of claims 1, 9 , 14 and 18 are of the present application, respectively. Also, they are both claiming the same subject matter of a multilayer coil array comprising coils with avoidance portions and lead-out conductors. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Application No. 18480932 Co-pending Application No. 18479292 Claim 1 Claim 1 A multilayer coil array comprising: an element body including a magnetic layer; a first coil inside the element body and including a plurality of first coil conductor layers in a stacking direction; a second coil inside the element body at a position further from a bottom surface of the element body than the first coil in the stacking direction and including a plurality of second coil conductor layers in the stacking direction; a first outer electrode and a second outer electrode on the bottom surface of the element body and electrically connected to the first coil; a third outer electrode and a fourth outer electrode on the bottom surface of the element body and electrically connected to the second coil; a first lead-out conductor inside the element body and connecting, out of end portions of the first coil, an end portion of the first coil conductor layer closest to the second coil and the first outer electrode to each other; a second lead-out conductor inside the element body and connecting another end portion of the first coil and the second outer electrode to each other; a third lead-out conductor inside the element body and connecting, out of end portions of the second coil, an end portion of the second coil conductor layer closest to the first coil and the third outer electrode to each other; and a fourth lead-out conductor inside the element body and connecting another end portion of the second coil and the fourth outer electrode to each other, wherein the first coil conductor layers include an avoidance portion inward or outward from the first lead-out conductor in plan view in the stacking direction so as to avoid two or more lead-out conductors including at least the first lead-out conductor, the second coil conductor layers include an avoidance portion inward or outward from the fourth lead-out conductor in plan view in the stacking direction so as to avoid the fourth lead-out conductor, and a width of the second coil conductor layers in parts other than the avoidance portion is larger than a width of the first coil conductor layers in parts other than the avoidance portion. A multilayer coil array comprising: an element body including a magnetic layer; a first coil inside the element body and including a plurality of first coil conductor layers in a stacking direction; a second coil inside the element body at a position further from a bottom surface of the element body than the first coil in the stacking direction and including a plurality of second coil conductor layers in the stacking direction; a first outer electrode and a second outer electrode on the bottom surface of the element body and electrically connected to the first coil; a third outer electrode and a fourth outer electrode on the bottom surface of the element body and electrically connected to the second coil; a first lead-out conductor inside the element body and connecting, out of end portions of the first coil, an end portion of the first coil conductor layer closest to the second coil and the first outer electrode to each other; a second lead-out conductor inside the element body and connecting another end portion of the first coil and the second outer electrode to each other; a third lead-out conductor inside the element body and connecting, out of end portions of the second coil, an end portion of the second coil conductor layer closest to the first coil and the third outer electrode to each other; and a fourth lead-out conductor inside the element body and connecting another end portion of the second coil and the fourth outer electrode to each other, wherein the first coil conductor layers include an avoidance portion and a straight portion connected to the avoidance portion, the avoidance portion being inward or outward from the first lead-out conductor in plan view in the stacking direction so as to avoid at least the first lead-out conductor, the second coil conductor layers include an avoidance portion and a straight portion connected to the avoidance portion, the avoidance portion being inward or outward from the fourth lead-out conductor in plan view in the stacking direction so as to avoid the fourth lead-out conductor, and a width of the first coil conductor layer in the avoidance portion in at least one location is smaller than a width of the first coil conductor layer in the straight portion, a width of the second coil conductor layer in the avoidance portion is smaller than a width of the second coil conductor layer in the straight portion, or a width of the first coil conductor layer in the avoidance portion in at least one location is smaller than a width of the first coil conductor layer in the straight portion and a width of the second coil conductor layer in the avoidance portion is smaller than a width of the second coil conductor layer in the straight portion. Claim 5 Claim 1 A multilayer coil array comprising: an element body including a magnetic layer; a first coil inside the element body and including a plurality of first coil conductor layers in a stacking direction; a second coil inside the element body at a position further from a bottom surface of the element body than the first coil in the stacking direction and including a plurality of second coil conductor layers in the stacking direction; a first outer electrode and a second outer electrode on the bottom surface of the element body and electrically connected to the first coil; a third outer electrode and a fourth outer electrode on the bottom surface of the element body and electrically connected to the second coil; a first lead-out conductor inside the element body and connecting, out of end portions of the first coil, an end portion of the first coil conductor layer closest to the second coil and the first outer electrode to each other; a second lead-out conductor inside the element body and connecting another end portion of the first coil and the second outer electrode to each other; a third lead-out conductor inside the element body and connecting, out of end portions of the second coil, an end portion of the second coil conductor layer closest to the first coil and the third outer electrode to each other; and a fourth lead-out conductor inside the element body and connecting another end portion of the second coil and the fourth outer electrode to each other, wherein the first coil conductor layers include an avoidance portion inward or outward from the first lead-out conductor in plan view in the stacking direction so as to avoid two or more lead-out conductors including at least the first lead-out conductor, the second coil conductor layers include an avoidance portion inward or outward from the fourth lead-out conductor in plan view in the stacking direction so as to avoid the fourth lead-out conductor, and a thickness from the bottom surface of the element body to the first coil in the stacking direction is greater than a thickness from a top surface, which is on an opposite side from the bottom surface, of the element body to the second coil. A multilayer coil array comprising: an element body including a magnetic layer; a first coil inside the element body and including a plurality of first coil conductor layers in a stacking direction; a second coil inside the element body at a position further from a bottom surface of the element body than the first coil in the stacking direction and including a plurality of second coil conductor layers in the stacking direction; a first outer electrode and a second outer electrode on the bottom surface of the element body and electrically connected to the first coil; a third outer electrode and a fourth outer electrode on the bottom surface of the element body and electrically connected to the second coil; a first lead-out conductor inside the element body and connecting, out of end portions of the first coil, an end portion of the first coil conductor layer closest to the second coil and the first outer electrode to each other; a second lead-out conductor inside the element body and connecting another end portion of the first coil and the second outer electrode to each other; a third lead-out conductor inside the element body and connecting, out of end portions of the second coil, an end portion of the second coil conductor layer closest to the first coil and the third outer electrode to each other; and a fourth lead-out conductor inside the element body and connecting another end portion of the second coil and the fourth outer electrode to each other, wherein the first coil conductor layers include an avoidance portion and a straight portion connected to the avoidance portion, the avoidance portion being inward or outward from the first lead-out conductor in plan view in the stacking direction so as to avoid at least the first lead-out conductor, the second coil conductor layers include an avoidance portion and a straight portion connected to the avoidance portion, the avoidance portion being inward or outward from the fourth lead-out conductor in plan view in the stacking direction so as to avoid the fourth lead-out conductor, and a width of the first coil conductor layer in the avoidance portion in at least one location is smaller than a width of the first coil conductor layer in the straight portion, a width of the second coil conductor layer in the avoidance portion is smaller than a width of the second coil conductor layer in the straight portion, or a width of the first coil conductor layer in the avoidance portion in at least one location is smaller than a width of the first coil conductor layer in the straight portion and a width of the second coil conductor layer in the avoidance portion is smaller than a width of the second coil conductor layer in the straight portion. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. A list of pertinent prior art is attached in form 892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kazi Hossain whose telephone number is 571-272-8182. The examiner can normally be reached on Monday-Thursday from Monday to Thursday 8:00 AM to 4:30 PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki Ismail can be reached at 571-272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAZI HOSSAIN/ Examiner, Art Unit 2837 /SHAWKI S ISMAIL/Supervisory Patent Examiner, Art Unit 2837
Read full office action

Prosecution Timeline

Oct 04, 2023
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+15.7%)
2y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 649 resolved cases by this examiner. Grant probability derived from career allowance rate.

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