DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/11/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maroney (U.S. Publication 2018/0032274), hereinafter Maroney.
Referring to claim 1, Maroney teaches, as claimed, a device (see Fig. 2, Data Storage Device 220), comprising:
a first interface (see Fig. 2; NAS Interface 243);
a memory (see Fig. 2, Non-Volatile Storage Components 245) configured in the device with the first interface to provide storage services (data storage system, see Paragraph 24) through the first interface to one or more apparatuses (see Fig. 2, Computing Device 213) that are external to the device (Note, Computing Device 213 and likes of them are external to Data Storage Device 220);
a second interface (see Fig. 2, DAS Interface 241) configured in the device to communicate with a processor (211 … maybe a laptop, see Paragraph 24; and Fig. 2, Computing Device 211) that is external to the device; and
a logic circuit (see Fig. 2. Controller 230, Fig. 3, Controller 230, and Fig. 4, Controller 230 (with Modules)) configured in the device to communicate via the second interface (see Fig. 5, Step 520; Note, a portion of Step 520 includes receiving first data access request from DAS which is the second interface) with the processor to process a portion of storage access messages (see Fig. 5, Step 520; Note, a portion of Step 520 includes receiving second data access request from NAS which is the first interface) received in the first interface.
Referring to claim 9, Maroney teaches, as claimed, method, comprising:
receiving, in a first interface (see Fig. 2; NAS Interface 243) of a device (see Fig. 2, Data Storage Device 220), storage access messages (see Fig. 5, Step 520; Note, a portion of Step 520 includes receiving first data access request from DAS which is the second interface) from one or more apparatuses (see Fig. 2, Computing Device 213) that are external to the device (Note, Computing Device 213 and likes of them are external to Data Storage Device 220);
communicating, by the device via a second interface (see Fig. 2, DAS Interface 241) of the device, with a processor (211 … maybe a laptop, see Paragraph 24; and Fig. 2, Computing Device 211) that is external to the device to process at least a portion of the storage access messages (see Fig. 5, Step 520; Note, a portion of Step 520 includes receiving second data access request from NAS which is the first interface) received in the first interface; and
providing, by the device using a memory (see Fig. 2, Non-Volatile Storage Components 245) of the device, storage services (data storage system, see Paragraph 24) to the one or more apparatuses (211 … maybe a laptop, see Paragraph 24; and Fig. 2, Computing Device 211) that are external to the device in response to the storage access messages.
Referring to claim 18, Maroney teaches, as claimed, a computing device (see Fig. 2, Data Storage Device 220), comprising:
a computer bus (see Fig. 2, DAS Interface 241);
a microprocessor (211 … maybe a laptop, see Paragraph 24; and Fig. 2, Computing Device 211) connected to the computer bus as a central processing unit (Note, a microprocessor used as a central processing unit is merely a descriptive language. Maroney also teaches a laptop which has a microprocessor that is used as a CPU); and
a storage product (see Fig. 3, Non-Volatile Storage Components 305) connected to the computer bus, the storage product comprising:
a memory (see Fig. 3, RAM 340); and
a network interface (see Fig. 3, NAS Interface 243);
wherein the storage product is configured to provide storage services over the network interface (see Fig. 1, Network 105).
As to claim 2, Maroney teaches the device of claim 1, wherein the device is manufactured as a computer component (see Fig. 2, Data Storage Device 220; Note, Controller 230 is not a CPU) having no central processing unit (executed by one or more general purpose or special purpose computers or processor, see Paragraph 61; Note, no specific requirement for central processing has been called out).
As to claim 3, Maroney teaches the device of claim 2, wherein the first interface is a network interface (see Fig. 2, Network 205); and the second interface is an interface (see Fig. 2, 250 to DAS Interface 241) to a computer bus (see Fig. 2, DAS Interface 212) connected to a central processing unit (211 … maybe a laptop, see Paragraph 24; and Fig. 2, Computing Device 211).
As to claim 4, Maroney teaches the device of claim 3, wherein the memory is configured to be accessible to the processor via the computer bus (see Fig.2 and Fig. 5) .
As to claim 5, Maroney teaches the device of claim 4, wherein the logic circuit is configured to identify (see Fig. 5, Step 505; Note, a Decision Diamond Shape identifies 3 different modes), among the storage access messages (see Fig. 5, Step 505; Note, 3 type of messages, Dual Mode, DAS Mode, and/or NAS Mode) received in the network interface, first messages (see Fig. 5, Step 520; Note, first two messages are Data access requests from DAS and NAS) and provide the first messages to the processor via the memory (Note, implicitly data written to Storages 245 whether it is via NAS or DAS, are available to processors of both NAS and DAS).
As to claim 6, Maroney teaches the device of claim 5, wherein the logic circuit is configured to process, among the storage access messages received in the network interface (see Fig. 2, NAS Interface 243), second messages (see Fig. 4, Step 530; Note, fourth data access request are implicitly many requests from network connected device that requires NAS storage access) without assistance from outside of the device (fully automated, see Paragraph 61).
As to claim 7, Maroney teaches the device of claim 6, wherein the device is configured as a solid-state drive (solid-state memory, see Paragraph 24) operable on the computer bus.
As to claim 8, Maroney teaches the device of claim 7, wherein the logic circuit is configured to convert packets (see Fig. 3, Translation Module 310) received in the network interface (see Fig. 3, NAS Interface) into the first messages (see Fig. 5, Step 520, First Data Access Request) and the second messages (see Fig. 5, Step 520, Second Data Access Request) based on a storage protocol (see Fig. 5, Dual Mode, DAS Mode, or NAS Mode) according to: internet small computer systems interface; fibre channel; fibre channel over ethernet; network file system (file-level data storage over a network, see Paragraph 12); or server message block.
As to claims 10-17 and 19-20, they are directed to a method/system to implement the device as set forth in claims 1-8. Therefore, they are rejected on the same basis as set forth hereinabove.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
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