CTNF 18/481,222 CTNF 89159 DETAILED ACTION This office action response to the communication filed on 10/04/2023. Claims 1-20 are presented for examination. Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (lDSs) submitted on October 04, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 8, 13, 15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shumsky et al. (U.S. Patent No. 9,996,468 B1), (“D1”, hereinafter), in view of Sangha et al. (U.S. Patent Application Publication No. 20020176430 A1), (“D2”, hereinafter) . As per Claim 1, D1 discloses an electronic apparatus ([see, Col. 3, 15-25, and Fig., 1, multi-core network device 100]), comprising: a processing unit ([see, Col. 2, 1-15, processing cores]); a buffer memory ([see, Col. 6, 8-15, and Fig., 2, the buffer memory 200]), having a plurality of packet buffer spaces ([see, Col. 10, lines 55-65, buffer space allocated to a single buffer packet, i.e., a packet that occupies only one buffer in the memory space 106]), wherein each of the packet buffer spaces is aligned to a packet size ([see, Col. 4, lines 19-25, Col. 6, lines 20-25, and Fig. 2, wherein the buffer memory has the multiple memory banks 204 of the buffer spaces that associated allows efficiently sized buffers]); and a buffer manager (see Fig. 1, the buffer manager 106); wherein each of the at least one available pointer is configured to mark a start address corresponding to a packet buffer space in the buffer memory ([see, Col. 6, lines 45-55, and Col. 7, 3-20, and Fig. 2, an indicator of or a pointer indicated to the buffer number 50 that the data packet 208 is stored in the buffer number 50]); the buffer manager is configured to monitor an available pointer quantity (register or table banks) and assign the at least one available pointer to the processing unit ([see, Col. 6, lines 45-55, and Col. 7, 3-20, and Fig. 2, and Col. 8, lines 25-35, and Fig. 4, a buffer manager 400 configured to manage a memory space shared by several client devices 410, 411 and the buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation… an allocation engine 402 accesses an appropriate free buffer queue 406 and retrieves an indication of (e.g., a pointer to) a free buffer from the head of the free buffer queue 406]) , wherein in response to that the processing unit transmits a first allocation request to the buffer manager ([see, Col. 4, lines 35-40, receiving a data packet to be stored in the memory space 104, transmits an allocation request 120 to the buffer manager 106]) and the available pointer quantity is sufficient ([see, Col. 6, lines 60-67, he table 300 includes 64 entries corresponding to the 64 buffers of the buffer memory 200 that necessary buffer used for storing a chunk or portion of a multi-buffer data packet]); the buffer manager is configured to obtain a first available pointer (the buffer 50) from the register, to update the available pointer quantity (table entry banks) ([see, Col. 7, lines 3-50, wherein a buffer manager 400 configured to manage a memory space, the pointer to indicated the buffer number 50 on the available pointer quantity, which is in our case table entry banks, and the table entry corresponding to the buffer number has update a link pointer for every buffer bank numbers]), the buffer manager (buffer manager 400) is configured to integrate the first available pointer and the available pointer quantity into a first allocation response and transmit the first allocation response to the processing unit ([see, Col. 5, lines 20-40, Col. 7, lines 3-67, wherein the buffer manager 106 is configured to receive and process allocation requests from several or all client devices 102, the buffer manager 106 is able to allocate respective memory portions in the memory device 104 (e.g., buffers) and indicate the respective allocated memory locations to the client devices 102 from which the allocation requests were received]). D1 doesn’t appear to explicitly disclose: a buffer manager comprising a register for temporarily storing at least one available pointer. However, D2 discloses a buffer manager comprising a register for temporarily storing ([see, [0046, 0076] and Fig. 5, Buffer manager 100 includes registers 260, one or more registers for temporarily storing data]) at least one available pointer ([see, [0060-0061], registers 260 to read an available data pointer]). In view of the above, having the system of D1 and then given the well-established teaching of D2, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D2. The motivation for doing so would have been to provide managing data packets in the register results enhanced the throughput of the buffer management system (D2, ¶ [0007]). As per Claims 8, 20, D1 further discloses transmits the first allocation request ([see, Col. 4, lines 35-40, receiving a data packet to be stored in the memory space 104, transmits an allocation request 120 to the buffer manager 106]). D1 appears to be silent to the instant claim, however D2 further discloses wherein and the available pointer quantity is insufficient, and in response to that the processing unit transmits the first allocation request and the available pointer quantity is insufficient, the buffer manager is configured to set a lower-bits portion of the first allocation response to be null or zero and transmit the first allocation response to the processing unit ([see, [0063], the memory space is 8 Megabytes, a 23-bit data pointer is sufficiently large to address the memory space. In accordance with one aspect of the system, the data buffers are aligned on 128-byte address boundaries. As a result, the 7 least significant bits of a 32-bit data pointer can be set to zero, for example, because they are not significant for memory addressing purposes]). In view of the above, having the system of D1 and then given the well-established teaching of D2, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D2. The motivation for doing so would have been to provide managing data packets in the register results enhanced the throughput of the buffer management system (D2, ¶ [0007]). As per Claim 13, D1 discloses an electronic apparatus ([see, Col. 3, 15-25, and Fig., 1, multi-core network device 100]), , comprising: a processing unit ([see, Col. 2, 1-15, processing cores]); a buffer memory ([see, Col. 6, 8-15, and Fig., 2, the buffer memory 200]), having a plurality of packet buffer spaces ([see, Col. 10, lines 55-65, buffer space allocated to a single buffer packet, i.e., a packet that occupies only one buffer in the memory space 106]), wherein each of the packet buffer spaces is aligned to a packet size ([see, Col. 4, lines 19-25, Col. 6, lines 20-25, and Fig. 2, wherein the buffer memory has the multiple memory banks 204 of the buffer spaces that associated allows efficiently sized buffers]); and a buffer manager (see Fig. 1, the buffer manager 106) , comprising wherein each of the at least one available pointer is configured to mark a start address corresponding to a packet buffer space in the buffer memory ([see, Col. 6, lines 45-55, and Col. 7, 3-20, and Fig. 2, an indicator of or a pointer indicated to the buffer number 50 that the data packet 208 is stored in the buffer number 50]) , the buffer manager is configured to monitor an available pointer quantity and assign the at least one available pointer to the processing unit ([see, Col. 6, lines 45-55, and Col. 7, 3-20, and Fig. 2, and Col. 8, lines 25-35, and Fig. 4, a buffer manager 400 configured to manage a memory space shared by several client devices 410, 411 and the buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation… an allocation engine 402 accesses an appropriate free buffer queue 406 and retrieves an indication of (e.g., a pointer to) a free buffer from the head of the free buffer queue 406]) , wherein the processing unit is configured to count a pending return pointer quantity ([see, Col. 12, lines 15-35, a number of indications that corresponds to the number free buffer queue]), to integrate a first available pointer and the pending return pointer quantity into a return request, and to transmit the return request to the buffer manager ([see, Col. 4, lines 35-40, receiving a data packet to be stored in the memory space 104, transmits an allocation request 120 to the buffer manager 106]) , in response to that the buffer manager receives the return request ([see, Col. 4, lines 40-65, and Fig. 1, the client device 102 sequentially transmits a corresponding number of allocation requests 120]), the buffer manager is configured to push the first available pointer into the register according to the return request and update the available pointer quantity ([see, Col. 4, lines 40-65, and Fig. 1, buffer manager 106 then transmits an allocation response 124 to the client device 102 from which the allocation request was received]) . D1 doesn’t appear to explicitly disclose: a buffer manager comprising a register for temporarily storing at least one available pointer. However, D2 discloses a buffer manager comprising a register for temporarily storing ([see, [0046, 0076] and Fig. 5, Buffer manager 100 includes registers 260, one or more registers for temporarily storing data]) at least one available pointer ([see, [0060-0061], registers 260 to read an available data pointer]). In view of the above, having the system of D1 and then given the well-established teaching of D2, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D2. The motivation for doing so would have been to provide managing data packets in the register results enhanced the throughput of the buffer management system (D2, ¶ [0007]). As per Claim 15, D1 discloses a control method, comprising: transmitting a first allocation request from a processing unit to a buffer manager ([see, Col. 4, lines 35-40, receiving a data packet to be stored in the memory space 104, transmits an allocation request 120 to the buffer manager 106]) ; determining by the buffer manager whether an available pointer quantity in a register is sufficient or not ([see, Col. 10, lines 55-67, wherein the buffer manager 400 to quickly clear buffer space for a higher number of multi-buffer data packets, checks validity of a clearing operation by determining whether the buffer being cleared is a buffer that is currently allocated]), in response to that the available pointer quantity is sufficient, obtaining a first available pointer from the register (table) by the buffer manager according to the first allocation request ([see, Col. 7, lines 3-50, wherein a buffer manager 400 configured to manage a memory space, the pointer to indicated the buffer number 50 on the available pointer quantity, which is in our case table entry banks, and the table entry corresponding to the buffer number has update a link pointer for every buffer bank numbers]), the first available pointer being configured to mark a start address of a packet buffer space ([see, Col. 6, lines 45-55, and Col. 7, 3-20, and Fig. 2, an indicator of or a pointer indicated to the buffer number 50 that the data packet 208 is stored in the buffer number 50]); updating the available pointer quantity within the register by the buffer manager ([see, Col. 4, lines 40-65, and Fig. 1, buffer manager 106 then transmits an allocation response 124 to the client device 102 from which the allocation request was received]); integrating the first available pointer and the available pointer quantity by the buffer manager for generating a first allocation response ([see, Col. 5, lines 20-40, Col. 7, lines 3-67, wherein the buffer manager 106 is configured to receive and process allocation requests from several or all client devices 102, the buffer manager 106 is able to allocate respective memory portions in the memory device 104 (e.g., buffers) and indicate the respective allocated memory locations to the client devices 102 from which the allocation requests were received]) ; and transmitting the first allocation response to the processing unit by the buffer manager ([see, Col. 4, lines 40-65, and Fig. 1, buffer manager 106 then transmits an allocation response 124 to the client device 102 from which the allocation request was received]) . D1 doesn’t appear to explicitly disclose: a buffer manager comprising a register for temporarily storing at least one available pointer. However, D2 discloses a buffer manager comprising a register for temporarily storing ([see, [0046, 0076] and Fig. 5, Buffer manager 100 includes registers 260, one or more registers for temporarily storing data]) at least one available pointer ([see, [0060-0061], registers 260 to read an available data pointer]). In view of the above, having the system of D1 and then given the well-established teaching of D2, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D2. The motivation for doing so would have been to provide managing data packets in the register results enhanced the throughput of the buffer management system (D2, ¶ [0007]). As per Claim 19, D1 and D2 disclose the control method of claim 15, and D1 further discloses wherein further comprising: counting a pending return pointer quantity by a communication transceiver unit ([see, Col. 12, lines 15-35, a number of indications that corresponds to the number free buffer queue]), wherein the communication transceiver unit is configured to integrate the first available pointer and the pending return pointer quantity into a first return request; transmitting the first return request from the communication transceiver unit to the buffer manager ([see, Col. 7, lines 50-67, Col. 8, lines 1-25, and Fig. 1-2, wherein the client device that issues memory allocation requests to the buffer manager 400, buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation, and Col. 8, lines 60-67, a first buffer type are allocated for data packets having a first priority level]) ; and pushing the first available pointer into the register by the buffer manager according to the first return request ([see, Col. 8, lines 1-30, and Fig. 1-2, the buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation]) . 07-21-aia AIA Claim s 2, 4-6, 9-12, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over D1, in view of D2, and further in view of Deutsch et al. (U.S. Patent Application Publication No. 2021/0240638), (“D3”, hereinafter) . As per Claims 2, 16, D1 doesn’t appear to explicitly disclose: wherein the buffer manager is configured to duplicate a higher-bits portion of the first available pointer as a higher-bits portion of the first allocation response, and the buffer manager is configured to record the available pointer quantity currently into a lower-bits portion of the first allocation response, so as to generate the first allocation response. However, D3 discloses wherein the buffer manager is configured to duplicate a higher-bits portion of the first available pointer as a higher-bits portion of the first allocation response, and the buffer manager is configured to record the available pointer quantity currently into a lower-bits portion of the first allocation response, so as to generate the first allocation response ([see, [0154-0156, 0227], and Fig. 9, wherein memory allocations, marker region 862 is evenly divided in the lower half of the slot and in the upper half of the slot, the lower bits of the pointer may be duplicated in the upper bits]). In view of the above, having the system of D1 and then given the well-established teaching of D3, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D3. The motivation for doing so would have been to provide managing bits portion of the slot results improve efficacy for the clearing memory with every memory allocation that enhanced the security vulnerabilities and increase memory safety to computing systems (D3, ¶ [0003]). As per Claims 4, 18, D1 further discloses wherein the processing unit is configured to obtain the first available pointer (a pointer to the buffer number 50) and a first packet buffer space in the buffer memory ( the table 300 includes 64 entries) corresponding to the first available pointer according to the higher-bits portion of the first allocation response ([see, Col. 6, lines 60-67, the table 300 includes 64 entries corresponding to the 64 buffers of the buffer memory 200 that necessary buffer used for storing a chunk or portion of a multi-buffer data packet]) , the processing unit is configured to write an outward-transmitting packet into the first packet buffer space ([see, Col. 7, lines 15-25, Col. 9, 55-67, and Col. 10, lines 1-10, and Fig. 2-3, wherein enable the buffer manager 400 to efficiently clear an entire buffer space allocated for storing a multi-buffer packet, the first chunk of the packet 210 is stored in the buffer number 57, and each following consecutive chunk of the packet 210 is stored in buffer numbers 20, 23, 11, and 59, respectively]). As per Claim 5, D1 and D2 disclose the electronic apparatus of claim 4, and D1 further discloses further comprising: a communication transceiver unit, configured to read the outward-transmitting packet from the first packet buffer space and transmit the outward-transmitting packet to an external network ([see, Col. 4, lines 55-65, and Fig. 1, wherein transmitted from the network device 100, a client device 102 couple to read 132-1-N with a read interface 132, and any client device 102 can then access the allocated buffer in the buffer memory 200 for writing packet data to and/or reading packet data from the buffer memory 200]), wherein in response to that the communication transceiver unit completes transmission of the outward-transmitting packet, the communication transceiver unit transmits a first return request to the buffer manager for returning the first available pointer ([see, Col. 7, lines 50-67, Col. 8, lines 1-25, and Fig. 1-2, wherein the client device that issues memory allocation requests to the buffer manager 400, buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation, and Col. 8, lines 60-67, a first buffer type are allocated for data packets having a first priority level]) , the buffer manager is configured to push the first available pointer into the register according to the first return request ([see, Col. 8, lines 1-30, and Fig. 1-2, the buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation]). As per Claim 6, D1 and D2 disclose the electronic apparatus of claim 5, and D1 further discloses wherein the communication transceiver unit is configured to count a pending return pointer quantity (free buffer size) ([see, Col. 12, lines 15-35, a number of indications that corresponds to the number free buffer queue]), to integrate the first available pointer and the pending return pointer quantity into the first return request and transmit the first return request to the buffer manager, the communication transceiver unit is configured to record the pending return pointer quantity currently into a lower-bits portion of the first return request, so as to generate the first return request ([see, Col. 4, lines 15-35, Col. 12, lines 15-35, and Fig. 1-30, wherein improve the speed and efficiency of buffer management, network device 100 is configured to efficiently utilize the memory space 104 for storing variable length packets received by the network device 100 by partitioning the memory space into a plurality of fixed-sized buffers and dynamically allocating the fixed-sized buffers to store a data packet based upon the size of the data packet]). D1 doesn’t appear to explicitly disclose: wherein the communication transceiver unit is configured to duplicate the higher-bits portion of the first available pointer as a higher-bits portion of the first return request. However, D3 further discloses wherein the communication transceiver unit is configured to duplicate the higher-bits portion of the first available pointer as a higher-bits portion of the first return request ([see, [0154-0156, 0227], and Fig. 9, wherein memory allocations, marker region 862 is evenly divided in the lower half of the slot and in the upper half of the slot, the lower bits of the pointer may be duplicated in the upper bits]). In view of the above, having the system of D1 and then given the well-established teaching of D3, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D3. The motivation for doing so would have been to provide managing bits portion of the slot results improve efficacy for the clearing memory with every memory allocation that enhanced the security vulnerabilities and increase memory safety to computing systems (D3, ¶ [0003]). As per Claim 9, D1 and D2 disclose the electronic apparatus of claim 1, and D1 further discloses further comprising: a communication transceiver unit ([see, Fig. 1), configured to receive an inward-transmitting packet from an external network ([see, Col. 3, lines 15-40, and Fig. 1, wherein buffer manager 106, receiving allocation requests from the client devices 102]); wherein in response to that the communication transceiver unit transmits a second allocation request to the buffer manager ([see, Col. 8, lines 25-45, and Fig. 4, client device that issues memory allocation requests to the buffer manager again to accesses an appropriate free buffer queue]) and the available pointer quantity is sufficient, the buffer manager is configured to obtain a second available pointer (free buffer) from the register (table) ([see, Col. 8, lines 25-45, Col. 9, lines 55-67, Col. 10, lines 1-10, and Fig. 4, wherein the buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation, and an appropriate free buffer queue disclosed]) and update the available pointer quantity ([see, Col. 8, lines 40-60, using ( update) a one of the free buffer queues 406 for subsequent allocations performed by the buffer manager 400]) ; and the buffer manager is configured to integrate of the second available pointer (next pointer) and the available pointer quantity (free pointer) into a second allocation response and transmit the second allocation response to the communication transceiver unit ([see, Col. 7, lines 50-67, Col. 8, lines 1-25, and Fig. 1-2, wherein the client device that issues memory allocation requests to the buffer manager 400, buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation, and Col. 8, lines 60-67, a first buffer type are allocated for data packets having a first priority level]) . D1 doesn’t appear to explicitly disclose: a higher-bits portion of the second available pointer. However, D3 further discloses a higher-bits portion of the second available pointer ([see, [0154-0156, 0227], and Fig. 9, wherein memory allocations, the upper bits of the pointer disclosed]). In view of the above, having the system of D1 and then given the well-established teaching of D3, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D3. The motivation for doing so would have been to provide managing bits portion of the slot results improve efficacy for the clearing memory with every memory allocation that enhanced the security vulnerabilities and increase memory safety to computing systems (D3, ¶ [0003]). As per Claim 10, D1 and D2 disclose the electronic apparatus of claim 9, and D1 further discloses wherein the communication transceiver unit ([see, Fig. 1), is configured to obtain the second available pointer (next pointer) and a second packet buffer space (free buffer) in the buffer memory corresponding to the second available pointer according to the second allocation response ([see, Col. 3, lines 15-40, and Fig. 1, wherein buffer manager 106, receiving allocation requests from the client devices 102]) , the communication transceiver unit is configured to write the inward-transmitting packet into the second packet buffer space ([see, Col. 7, lines 50-67, Col. 8, lines 1-25, and Fig. 1-2, wherein the client device that issues memory allocation requests to the buffer manager 400, buffer manager 400 maintains a free buffer pool to store indications of buffers currently available for allocation, and Col. 8, lines 60-67, a first buffer type are allocated for data packets having a first priority level]) . D1 doesn’t appear to explicitly disclose: the second available pointer according to the higher-bits portion of the second allocation response. However, D3 further discloses the second available pointer according to the higher-bits portion of the second allocation response ([see, [0154-0156, 0227], and Fig. 9, wherein memory allocations, the upper bits of the pointer disclosed]). In view of the above, having the system of D1 and then given the well-established teaching of D3, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D3. The motivation for doing so would have been to provide managing bits portion of the slot results improve efficacy for the clearing memory with every memory allocation that enhanced the security vulnerabilities and increase memory safety to computing systems (D3, ¶ [0003]). As per Claim 11, D1 and D2 disclose the electronic apparatus of claim 10, and D1 further discloses wherein the processing unit is configured to read the inward-transmitting packet from the second packet buffer space ([see, Col. 4, lines 55-65, and Fig. 1, the client device read data packet via a read interface 132]) , in response to that the processing unit completes reading the inward-transmitting packet, the processing unit transmits a second return request to the buffer manager for returning the second available pointer ([see, Col. 4, lines 40-65, and Fig. 1, the client device 102 sequentially transmits a corresponding number of allocation requests 120]) , the buffer manager is configured to push the second available pointer into the register according to the second return request ([see, Col. 4, lines 40-65, and Fig. 1, buffer manager 106 then transmits an allocation response 124 to the client device 102 from which the allocation request was received]) . As per Claim 12, D1 and D2 disclose the electronic apparatus of claim 11, and D1 further discloses wherein the processing unit is configured to count a pending return pointer quantity and to generate the second return request ([see, Col. 12, lines 15-35, a number of indications that corresponds to the number free buffer queue]), the processing unit is configured to integrate the second available pointer and the pending return pointer quantity into the second return request and transmit the second return request to the buffer manager ([see, Col. 6, lines 20-40, the buffer group 202-1 includes a second set of buffers that includes second available pointer, and on Col. 4, lines 40-65, and Fig. 1, the client device 102 sequentially transmits a corresponding number of allocation requests 120]). D1 doesn’t appear to explicitly disclose: wherein the processing unit is configured to duplicate the higher-bits portion of the second available pointer as a higher-bits portion of the second return request; and the processing unit is configured to record the pending return pointer quantity currently into a lower-bits portion of the second return request. However, D3 further discloses wherein the processing unit is configured to duplicate the higher-bits portion of the second available pointer as a higher-bits portion of the second return request ([see, [0154-0156, 0227], and Fig. 9, wherein memory allocations, marker region 862 is evenly divided in the lower half of the slot and in the upper half of the slot, the lower bits of the pointer may be duplicated in the upper bits]); and the processing unit is configured to record the pending return pointer quantity currently into a lower-bits portion of the second return request ([see, [0227], and Fig. 9, the lower bits of the pointer disclosed]). In view of the above, having the system of D1 and then given the well-established teaching of D3, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D3. The motivation for doing so would have been to provide managing bits portion of the slot results improve efficacy for the clearing memory with every memory allocation that enhanced the security vulnerabilities and increase memory safety to computing systems (D3, ¶ [0003]) . 07-21-aia AIA Claim s 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over D1, in view of D2, in view of D3, and further in view of Pais et al. (U.S. Patent Application Publication No. 2013/0088965), (“D4”, hereinafter) As per Claims 3, 17, D1 doesn’t appear to explicitly disclose: wherein the processing unit is configured to obtain the available pointer quantity (entry banks) according to the lower-bits portion of the first allocation response, in response to that the available pointer quantity is lower than a threshold value, the processing unit temporarily stops transmitting another allocation request or reduces a frequency of transmitting the another allocation request. However, D4 discloses wherein the processing unit is configured to obtain the available pointer quantity (entry banks) according to the lower-bits portion of the first allocation response, in response to that the available pointer quantity is lower than a threshold value, the processing unit temporarily stops transmitting another allocation request or reduces a frequency of transmitting the another allocation request ([see, [0006, 0028], wherein the managing a plurality of buffer addresses, a controller configured to monitor a number of unassigned buffer pointers, and if the number of unassigned buffer pointers in falls below a threshold value, allocate one or more buffer pointers from an external buffer pointer pool]). In view of the above, having the system of D1 and then given the well-established teaching of D4, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D4. The motivation for doing so would have been to provide managing bits portion of the slot results improve efficacy for the clearing memory with every memory allocation that enhanced the security vulnerabilities and increase memory safety to computing systems (D4, ¶ [0003]) . 07-21-aia AIA Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over D1, in view of D2, in view of D3, and further in view of Roh et al. (U.S. Patent Application Publication No. 2005/0080929), (“D5”, hereinafter) . As per Claim 7, D1, D2 and D3 disclose the electronic apparatus of claim 6, and D1 doesn’t appear to explicitly disclose: wherein the buffer manager is configured to obtain the pending return pointer quantity according to the lower-bits portion of the first return request, in response to that a sum of the pending return pointer quantity and the available pointer quantity is greater than a maximal accommodation volume of the register (table), the buffer manager is configured to transmit a warning signal to the communication transceiver unit. However, D5 discloses wherein the buffer manager (buffer manager 140) is configured to obtain the pending return pointer quantity according to the lower-bits portion of the first return request ([see, [0016-0017], wherein a buffer manager for detecting an overflow of the buffer storing the data, detecting a position of a memory pointer of the double buffer and determining whether or not a buffer overflow]), in response to that a sum of the pending return pointer quantity and the available pointer quantity is greater than a maximal accommodation volume of the register (table), the buffer manager is configured to transmit a warning signal to the communication transceiver unit ([see, [0021, 0037], a buffer manager 140 for detecting an overflow of the buffer 132 storing the data encoded by the encoder 130 and issuing a control signal for pausing an encoding operation when the overflow is detected]). In view of the above, having the system of D1 and then given the well-established teaching of D5, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D5. The motivation for doing so would have been to provide a buffer manager capable of automatically pausing results improve transmission delay at the server device transmitting predetermined data to a client device and an overflow of data due to the transmission delay (D5, ¶ [0002]) . 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over D1, in view of D2, and further in view of Roh et al. (U.S. Patent Application Publication No. 2005/0080929), (“D5”, hereinafter) . As per Claim 14, D1, and D2 disclose the electronic apparatus of claim 13, and D1 doesn’t appear to explicitly disclose: wherein in response to that the buffer manager receives the return request, the buffer manager is configured to check whether a sum of the pending return pointer quantity and the available pointer quantity is greater than a maximal accommodation volume of the register, in response to that the sum is greater than the maximal accommodation volume, the buffer manager transmits a warning signal to the processing unit . However, D5 discloses wherein in response to that the buffer manager receives the return request, the buffer manager is configured to check whether a sum of the pending return pointer quantity and the available pointer quantity is greater than a maximal accommodation volume of the register ([see, [0016-0017], wherein a buffer manager for detecting an overflow of the buffer storing the data, detecting a position of a memory pointer of the double buffer and determining whether or not a buffer overflow]), in response to that the sum is greater than the maximal accommodation volume, the buffer manager transmits a warning signal to the processing unit ([see, [0021, 0037], a buffer manager 140 for detecting an overflow of the buffer 132 storing the data encoded by the encoder 130 and issuing a control signal for pausing an encoding operation when the overflow is detected]). In view of the above, having the system of D1 and then given the well-established teaching of D5, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the system of D1 as taught by D5. The motivation for doing so would have been to provide a buffer manager capable of automatically pausing results improve transmission delay at the server device transmitting predetermined data to a client device and an overflow of data due to the transmission delay (D5, ¶ [0002]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BERHANU BELETE whose telephone number is (571)272-3478. The examiner can normally be reached on Monday-Friday 7:30am-5pm, Alt. Friday, and EDT. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ASAD NAWAZ can be reached on (571)272-3988. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BERHANU D BELETE/ Examiner, Art Unit 2468 /WUTCHUNG CHU/Primary Examiner, Art Unit 2418 Application/Control Number: 18/481,222 Page 2 Art Unit: 2418 Application/Control Number: 18/481,222 Page 4 Art Unit: 2418 Application/Control Number: 18/481,222 Page 5 Art Unit: 2418 Application/Control Number: 18/481,222 Page 6 Art Unit: 2418 Application/Control Number: 18/481,222 Page 7 Art Unit: 2418 Application/Control Number: 18/481,222 Page 8 Art Unit: 2418 Application/Control Number: 18/481,222 Page 9 Art Unit: 2418 Application/Control Number: 18/481,222 Page 10 Art Unit: 2418 Application/Control Number: 18/481,222 Page 11 Art Unit: 2418 Application/Control Number: 18/481,222 Page 12 Art Unit: 2418 Application/Control Number: 18/481,222 Page 13 Art Unit: 2418 Application/Control Number: 18/481,222 Page 14 Art Unit: 2418 Application/Control Number: 18/481,222 Page 15 Art Unit: 2418 Application/Control Number: 18/481,222 Page 16 Art Unit: 2418 Application/Control Number: 18/481,222 Page 17 Art Unit: 2418 Application/Control Number: 18/481,222 Page 18 Art Unit: 2418 Application/Control Number: 18/481,222 Page 19 Art Unit: 2418 Application/Control Number: 18/481,222 Page 20 Art Unit: 2418 Application/Control Number: 18/481,222 Page 21 Art Unit: 2418 Application/Control Number: 18/481,222 Page 22 Art Unit: 2418 Application/Control Number: 18/481,222 Page 23 Art Unit: 2418 Application/Control Number: 18/481,222 Page 24 Art Unit: 2418