DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-9 and 15-20 in the reply filed on 08 January 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 7, 15 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kalnitsky et al. US 9,178,080.
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Regarding claim 1, Kalnitsky et al. in Fig. 11 discloses a capacitor structure comprising a moat capacitor embedded in a substrate 300, the moat capacitor includes:
a bottom electrode plate 400;
a dielectric layer 600 directly above and lining the bottom electrode plate 400; and
a top electrode plate 700 directly above and lining the dielectric layer 600,
wherein the bottom electrode plate 400, the dielectric layer 600, and the top electrode plate 700 have encircling shapes and are arranged to be concentric with one another.
Regarding claim 2, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 1, wherein the top electrode plate 700 has a U-shaped cross-section;
the dielectric layer 600 surrounds a bottom and sides of the top electrode plate 700; and
the bottom electrode plate 400 surrounds a bottom and sides of the dielectric layer 600.
Regarding claim 3, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 2, wherein the moat capacitor further includes a filler layer 900 on top of the top electrode plate 700, the filler layer 900 filling a space between an inner edge and an outer edge of the top electrode plate 700.
Regarding claim 7, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 1, wherein the moat capacitor is a first moat capacitor, further comprising a second moat capacitor nested inside the first moat capacitor, wherein the second moat capacitor has a bottom electrode plate 400 that merges with the bottom electrode plate 400 of the first moat capacitor.
Regarding claim 15, Kalnitsky et al. in Fig. 11 discloses a capacitor structure comprising a moat capacitor, the moat capacitor includes:
a bottom electrode plate 400 formed in an encircling shape;
a dielectric layer 600 directly above and formed along the bottom electrode plate 400; and
a top electrode plate 700 directly above and formed along the dielectric layer 600.
Regarding claim 19, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 15, wherein the moat capacitor is a first moat capacitor, further comprising a second moat capacitor nested inside the first moat capacitor, wherein the second moat capacitor has a bottom electrode plate 400 that merges with the bottom electrode plate 400 of the first moat capacitor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kalnitsky et al. US 9,178,080.
Regarding claim 5, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 1 but does not expressly disclose wherein the encircling shape of the dielectric layer 600 is a square shape and the moat capacitor has a length and a width, wherein the length is at least 10 times larger than the width.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 6, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 1 but does not expressly disclose wherein the dielectric layer 600 has a U-shaped cross-section and the moat capacitor has a depth and a width, wherein the depth is at least 25 times larger than the width.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 18, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 1 but does not expressly disclose wherein the moat capacitor has a square shape and a length, a width, and a depth, wherein the length is at least 10 times larger than the width and the depth is at least 25 times larger than the width.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Claim(s) 8, 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kalnitsky et al. as applied to claims 1 and 15 above, and further in view of Chuang et al. US 9,679,909.
Regarding claim 8, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 1 but does not expressly disclose the capacitor structure of claim 1 further comprising an isolation trench embedded in the substrate, wherein the isolation trench encircles the moat capacitor.
Chuang et al. teaches a semiconductor substrate including a memory cell region 106, a logic region 114 and a capacitor region 108. The semiconductor substrate further includes isolation trenches that encircles a trench capacitor to isolate the regions 106, 114 and 108 from each other.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chuang et al. in the device of Kalnitsky et al. for the purpose of integrating different semiconductor components of a semiconductor device into a common semiconductor structure and allowing for increased operational speed.
Regarding claim 9, Kalnitsky et al. in view of Chuang et al. teaches the capacitor structure of claim 8, but does not expressly disclose wherein the isolation trench has a depth that is larger than a depth of the moat capacitor.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 20, Kalnitsky et al. in Fig. 11 discloses the capacitor structure of claim 15 but does not expressly disclose the capacitor structure of claim 15 further comprising an isolation trench embedded in the substrate, wherein the isolation trench encircles the moat capacitor.
Chuang et al. teaches a semiconductor substrate including a memory cell region 106, a logic region 114 and a capacitor region 108. The semiconductor substrate further includes isolation trenches that encircles a trench capacitor to isolate the regions 106, 114 and 108 from each other.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chuang et al. in the device of Kalnitsky et al. for the purpose of integrating different semiconductor components of a semiconductor device into a common semiconductor structure and allowing for increased operational speed.
Allowable Subject Matter
Claims 4, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following are statements of reasons for the indication of allowable subject matter:
4. (Original) The capacitor structure of claim 1, further comprising a capping layer above the substrate and the moat capacitor, a first set of contacts embedded in the capping layer in contact with the top electrode plate and a second and a third set of contacts embedded in the capping layer in contact with an inner edge and an outer edge respectively of the bottom electrode plate.
16. (Original) The capacitor structure of claim 15, wherein the moat capacitor further includes a filler layer on top of the top electrode plate, filling a space between an inner edge and an outer edge of the top electrode plate, and a landing pad above the filler layer and in contact with the inner edge and the outer edge of the top electrode plate.
17. (Original) The capacitor structure of claim 16, further comprising a first set of contacts in contact with the top electrode plate via the landing pad, and a second and a third set of contacts in contact with an inner edge and an outer edge respectively of the bottom electrode plate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898