DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 2013/03/16, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW 112103729 , filed on 2023/02/02.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: A title that states the inventive concept of this/these particular CONTROL DEVICE, CONTROL SIGNAL GENERATION METHOD, AND VOLTAGE CONVERSION DEVICE, which distinguishes it/them from other CONTROL DEVICES, CONTROL SIGNAL GENERATION METHODS, AND VOLTAGE CONVERSION DEVICES.
The abstract of the disclosure is objected to because
The abstract introduces "the battery signal" (with definite article) without antecedent. The abstract should read "a battery signal" at first reference.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3, 5, 15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3, 15 recite the limitation "the third voltage". There is insufficient antecedent basis for this limitation in the claim. The established claim term (from Claim 1) is "third level voltage."
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1 – 5, 7 – 8, 13 – 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA et al. (US 4,750,056 A), and further in view of CHOO (US 6,163,086 A).
In re claim 1, OGAWA discloses a control device, comprising (col. 1, ll. 5–6; FIG. 1: power circuit for a recording unit):
a delay circuit (FIG. 1; resistor 9 (R9) in series with capacitor 10 (C10) between collector of transistor 1 and ground) configured to generate a delay signal (voltage at terminal C of flip-flop 8 connected to R9/C10 junction) based on a power signal (voltage at terminal D connected to collector of transistor 1), wherein when the power signal is changed from a first level voltage to a second level voltage, the delay signal reaches the second level voltage later than the power signal (col. 2, ll. 10 – 12: C10 charges through R9 after the power signal rises); and
an output circuit (flip-flop 8) configured to receive the power signal, the delay signal, wherein when the delay signal is changed from the first level voltage to the second level voltage, the output circuit outputs a level voltage of the power signal which is received (col. 2, ll. 10–12: when terminal C transitions low-to-high while terminal D is high, terminal Q captures D's level), and the output circuit outputs a stopping voltage (col. 2, ll. 3–5: assertion of reset terminal R forces Q to a defined low level).
OGAWA is silent to a logic circuit configured to receive the power signal and a battery signal, wherein an output end of the logic circuit outputs a third level voltage in response to that one of the power signal and the battery signal is at the second level voltage, and a fourth level voltage in response to that both of the power signal and the battery signal are at the first level voltage.
CHOO teaches a logic circuit (voltage level adjusting circuit 400) configured to receive the power signal and a battery signal (FIG. 6: diode D402 coupled to node N400 and adapter-supplied voltage Vadp; diode D401 coupled to node N400 and battery-supplied voltage Vbat), wherein an output end of the logic circuit outputs a third level voltage in response to that one of the power signal and the battery signal is at the second level voltage (node N400 pulled “high” through D401 or D402 when Vadp or Vbat is “high”), and a fourth level voltage in response to that both of the power signal and the battery signal are at the first level voltage (node N400 pulled “low” when both Vadp and Vbat are “low”).
It would have been obvious for a person having ordinary skill in the art (PHOSITA) to incorporate CHOO's diode wired-OR logic circuit into OGAWA's control device framework, with node N400 connected to the reset terminal R of OGAWA's flip-flop 8, to provide the control device's output circuit with a constant voltage regardless of the power sources.
In re claims 2, 14, OGAWA discloses wherein the output circuit comprises a first end, a second end, and a third end (flip flop 8’s terminals D, C, R), the first end receives the power signal (terminal D connected to collector of transistor 1), the second end receives the delay signal (terminal C connected to R9/C10 junction).
OGAWA is silent to the third end is connected to the output end of the logic circuit to receive the output signal of the output end of the logic circuit.
CHOO teaches the logic circuit (voltage level adjusting circuit 400).
It would have been obvious for a PHOSITA to connect CHOO's diode wired-OR logic circuit to the third end of OGAWA's output circuit, and receive the output signal of the output end of the logic circuit by the third end, to provide the control device's output circuit with a constant voltage regardless of the power sources.
In re claims 3, 15, OGAWA discloses wherein the first level voltage and the stopping voltage are each a low voltage (col. 2, ll. 10–12; ll. 3–5: “terminal C of the flip-flop [8] goes from a low level to a high level”; terminal R assertion resets inherently resets Q), and the second level voltage and the third voltage are each a high voltage (col. 2, ll. 10–15: “the terminal Q is changed from a low level to high level because the terminal D is at a high level”).
OGAWA is silent to the fourth level voltage is at a low voltage, and the third voltage is a high voltage.
CHOO teaches the fourth level voltage is at a low voltage (FIG. 6: node N400 is low level when both Vadp and Vbat high level), and the third voltage is a high voltage (FIG. 6: node N400 is high level when either Vadp or Vbat is high level).
It would have been obvious for a PHOSITA to incorporate CHOO's diode wired-OR logic circuit into OGAWA's control device framework to provide the control device's output circuit with a constant voltage regardless of the power sources.
In re claim 4, OGAWA discloses wherein the output circuit is a positive edge triggered D-flip flop (terminal Q captures terminal D’s level when terminal C goes from a low level to a high level), a signal input end of the positive edge triggered D-flip flop is the first end (FIG. 1: terminal D receives signal input), a clock input end of the positive edge triggered D-flip flop is the second end (terminal C), and a clear end of the positive edge triggered D-flip flop is the third end (terminal R).
In re claims 5, 16, OGAWA is silent to wherein the logic circuit comprises a first forward conducting element, a second forward conducting element, and a grounding circuit; a first end of the first forward conducting element receives the power signal, the first forward conducting element is in a conduction state when the power signal is at the high voltage, and the first forward conducting element is in a non-conduction state when the power signal is at the low voltage; a first end of the second forward conducting element receives the battery signal, the second forward conducting element is in the conduction state when the battery signal is at the high voltage, and the second forward conducting element is in the non-conduction state when the battery signal is at the low voltage; a second end of the first forward conducting element is connected to a second end of the second forward conducting element, the third end of the output circuit, and a first end of the grounding circuit, and a second end of the grounding circuit is connected to a ground end; and a voltage of the first end of the grounding circuit is taken as an output of the output end of the logic circuit.
CHOO teaches wherein the logic circuit comprises (voltage level adjusting circuit 400) a first forward conducting element (diode D402), a second forward conducting element (diode D401), and a grounding circuit (variable resistance circuit 405);
a first end of the first forward conducting element receives the power signal (FIG. 6: D402's anode coupled to Vadp), the first forward conducting element is in a conduction state when the power signal is at the high voltage (FIG. 6: D402 conducts when Vadp is “high”), and the first forward conducting element is in a non-conduction state when the power signal is at the low voltage (FIG. 6: D402 does not conduct when Vadp is “low”);
a first end of the second forward conducting element receives the battery signal (FIG. 6: D401's anode coupled to Vbat), the second forward conducting element is in the conduction state when the battery signal is at the high voltage (FIG. 6: D401 conducts when Vbat is “high”), and the second forward conducting element is in the non-conduction state when the battery signal is at the low voltage (FIG. 6: D401 does not conduct when Vbat is “low”);
a second end of the first forward conducting element is connected to a second end of the second forward conducting element and a first end of the grounding circuit, and a second end of the grounding circuit is connected to a ground end (FIG. 6: N400 connects variable resistance circuit 405 to cathodes of both D401 and D402; variable resistance circuit 405 connected to ground voltage VSS); and
a voltage of the first end of the grounding circuit is taken as an output of the output end of the logic circuit (FIG. 6: node N400 is first end of variable resistance circuit).
It would have been obvious for a PHOSITA to connect CHOO's diode wired-OR logic circuit to the third end of OGAWA's output circuit to provide the control device's output circuit with a constant voltage regardless of the power sources.
In re claim 7, OGAWA is silent to wherein the first forward conducting element is a first diode, an anode of the first diode is the first end of the first forward conducting element, and a cathode of the first diode is the second end of the first forward conducting element; and the second forward conducting element is a second diode, an anode of the second diode is the first end of the second forward conducting element, and a cathode of the second diode is the second end of the second forward conducting element.
CHOO teaches wherein the first forward conducting element is a first diode, an anode of the first diode is the first end of the first forward conducting element, and a cathode of the first diode is the second end of the first forward conducting element (FIG. 6: D402 with anode coupled to Vadp and cathode coupled to N400); and
the second forward conducting element is a second diode, an anode of the second diode is the first end of the second forward conducting element, and a cathode of the second diode is the second end of the second forward conducting element (FIG. 6: D401 with anode coupled to Vbat and cathode coupled to N400).
It would have been obvious for a PHOSITA to incorporate CHOO's diode wired-OR logic circuit into OGAWA's control device framework to provide the control device's output circuit with a constant voltage regardless of the power sources.
In re claims 8, 18, OGAWA discloses wherein the first level voltage is a low voltage, the second level voltage is a high voltage (col. 2, ll. 10–20: power signal transitions from a low level to a high level), the delay circuit comprises a resistive element (R9) and a capacitive element (C10), a first end of the resistive element receives the power signal (FIG. 1: first end of R9 connected to collector of transistor 1), a second end of the resistive element is connected to a first end of the capacitive element and the second end of the output circuit (FIG. 1: second end of R9 connected to first end of C10, flip flop 8’s terminal C), and a second end of the capacitive element is connected to a grounding end (FIG. 1: second end of C10 connected to ground).
As to claim 18, OGAWA further discloses the capacitive element receives the power signal through the resistive element (FIG. 1: C10 charged through R9), and the step (a) comprises: taking a capacitor voltage signal of the first end of the capacitive element which receives the power signal as the delay signal (FIG. 1: terminal C, first end of C10).
In re claim 13, OGAWA discloses a control signal generation method, adapted for a control device (Abstract: method of operating the power circuit for a recording unit) comprising a delay circuit (R9, C10), and an output circuit (flip flop 8), wherein the control signal generation method comprises:
(a) generating a delay signal by the delay circuit based on a power signal (FIG. 1: R9, C10 generates terminal C voltage from the transistor 1), wherein when the power signal is changed from a first level voltage to a second level voltage, the delay signal reaches the second level voltage later than the power signal (col. 2, ll. 10–20: C10 charges through R9 after the power signal rises); and
(c) receiving the power signal and the delay signal by the output circuit (FIG. 1: flip-flop 8 receives power signal at terminal D, delay signal at terminal C); when the delay signal is changed from the first level voltage to the second level voltage, outputting a level voltage of the power signal which is received by the output circuit (col. 2, ll. 10–20); and outputting a stopping voltage by the output circuit (col. 2, ll. 3–9).
OGAWA is silent to a logic circuit, (b) receiving the power signal and a battery signal by the logic circuit; outputting a third level voltage by an output end of the logic circuit in response to that one of the power signal and the battery signal is at the second level voltage; and outputting a fourth level voltage by the output end of the logic circuit in response to that both of the power signal and the battery signal are at the first level voltage; receiving an output signal outputted by the output end of the logic circuit.
CHOO teaches a logic circuit (voltage level adjusting circuit 400),
(b) receiving the power signal and a battery signal by the logic circuit (FIG. 6: N400 receives Vadp through D402, Vbat through D401); outputting a third level voltage by an output end of the logic circuit in response to that one of the power signal and the battery signal is at the second level voltage (FIG. 6: node N400 is high level when either Vadp or Vbat is high level); outputting a fourth level voltage by the output end of the logic circuit in response to that both of the power signal and the battery signal are at the first level voltage (FIG. 6: node N400 is low level when both Vadp and Vbat high level); and
receiving an output signal outputted by the output end of the logic circuit (FIG. 6: N400 receives signal from D402, D401).
It would have been obvious for a PHOSITA to incorporate CHOO's diode wired-OR logic into OGAWA's control method framework to provide the control device's output circuit with a constant voltage regardless of the power sources.
Claim(s) 6, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA et al. (US 4,750,056 A), CHOO (US 6,163,086 A), and further in view of IKETANI et al. (US 5,703,510 A).
In re claims 6, 17, OGAWA is silent to wherein the grounding circuit comprises a resistive element and a capacitive element, a first end of the capacitive element and a first end of the resistive element are connected to the first end of the grounding circuit, and a second end of the capacitive element and a second end of the resistive element are connected to the second end of the grounding circuit.
IKETANI teaches the grounding circuit comprises a resistive element (resistance element 21 (R21)) and a capacitive element (capacitor 15 (C15)), a first end of the capacitive element and a first end of the resistive element are connected to the first end of the grounding circuit (FIG. 2: R21, C15 connected at node NA), and a second end of the capacitive element and a second end of the resistive element are connected to the second end of the grounding circuit (FIG. 2: R21, C15 connected to ground voltage VSS).
As to claim 17, IKETANI further teaches the step (b) comprises: taking a voltage of the first end of the resistive element as the voltage of the first end of the grounding circuit (FIG. 2: voltage VA at node NA).
It would have been obvious for a PHOSITA to use IKETANI’s grounding circuit in OGAWA’s control device framework to ensure that the power-on reset signal can be surely generated even when the power is again turned on, by providing complete discharge of the capacitor through the resistance element when power is turned off.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA et al. (US 4,750,056 A), CHOO (US 6,163,086 A), and further in view of SAITOH (US 4,900,949 A).
In re claims 9, 19, OGAWA is silent to wherein the delay circuit comprises a buffer gate element, a first end of the buffer gate element receives the power signal, and a second end of the buffer gate element is connected to the second end of the output circuit.
SAITOH teaches the delay circuit comprises a buffer gate element (inverter INV), a first end of the buffer gate element receives the power signal (FIG. 4: input of inverter INV receives clock signal CP), and a second end of the buffer gate element is connected to the second end of the output circuit (FIG. 4: output of inverter INV connects master F.F.).
As to claim 19, SAITOH further teaches the step (a) comprises: taking a buffer gate output voltage signal of the second end of the buffer gate element which receives the power signal as the delay signal (col. 2, ll. 50–55: master F.F input delayed Td(INV)).
It would have been obvious for a PHOSITA to substitute SAITOH's buffer gate delay element for OGAWA's RC delay circuit to reduce the total propagation delay time and realize a high speed operation without increasing a power dissipation.
Claim(s) 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA et al. (US 4,750,056 A), CHOO (US 6,163,086 A), and further in view of DIMASSIMO et al. (US 4,342,922 A).
In re claims 10, 20, OGAWA is silent to a first resistive element and a second resistive element, wherein the first resistive element receives an electronic device power signal through a first end of the first resistive element, bucks down the electronic device power signal, and outputs the electronic device power signal which has been bucked down from a second end of the first resistive element as the power signal; the second resistive element receives an electronic device battery signal through a first end of the second resistive element, bucks down the electronic device battery signal, and outputs the electronic device battery signal which has been bucked down from a second end of the second resistive element as the battery signal.
DIMASSIMO teaches a first resistive element (voltage divider of resistors 20 (R20) and 21 (R21)) and a second resistive element (resistor 15 (R15)), wherein
the first resistive element receives an electronic device power signal through a first end of the first resistive element (col. 3, ll. 19: “The free end of resistor 21 connects to bus VC…”), bucks down the electronic device power signal, and outputs the electronic device power signal which has been bucked down from a second end of the first resistive element as the power signal (col. 3, ll. 15–25: R21/R20 junction outputs stepped-down voltage to transistor 18);
the second resistive element receives an electronic device battery signal through a first end of the second resistive element (col. 3, ll. 10–15: first end of R15 coupled to anode of battery B1), bucks down the electronic device battery signal, and outputs the electronic device battery signal which has been bucked down from a second end of the second resistive element as the battery signal (col. 3, ll. 10–15: second end of R15 connects to base of transistor 18, providing a stepped-down battery-derived voltage).
It would have been obvious for a PHOSITA to add DIMASSIMO's first and second resistive elements as input-side signal conditioning resistors for OGAWA’s control device framework to provide a power supply with reliable means to detect the failure of an AC power source and error-free switchover circuitry to supply emergency power from a standby battery.
Claim(s) 11 – 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over OGAWA et al. (US 4,750,056 A), CHOO (US 6,163,086 A), and further in view of COOK et al. (US 11,070,077 B2).
In re claims 11 – 12, OGAWA is silent to a voltage conversion device further comprising: a monitoring element configured to monitor whether a battery of an electronic device is supplying power and output a battery usage signal based on an output voltage of the battery of the electronic device; and a DC conversion element configured to convert the output voltage provided by the battery in response to that the output circuit of the control device outputs a starting voltage and stop converting the output voltage provided by the battery in response to that the output circuit of the control device outputs the stopping voltage; wherein the control device generates the battery signal based on the battery usage signal, and the control device generates the power signal based on a power input signal of the electronic device.
COOK teaches a voltage conversion device (FIG. 1: electronic device with hibernate control circuit 10 and boost regulator 26) further comprising:
a monitoring element configured to monitor whether a battery of an electronic device is supplying power (col. 4, ll. 23–35: hibernate set logic 12 couples to battery voltage sensor) and output a battery usage signal based on an output voltage of the battery of the electronic device (col. 4, ll. 23–35: state controller 20 generates hibernate enable signal 31); and
a DC conversion element (boost regulator 26) configured to convert the output voltage provided by the battery in response to that the output circuit of the control device outputs a starting voltage (col. 3, ll. 20–25: “… a boost regulator 26 can be provided to boost the battery voltage Vbat up to the voltage that the hibernatable circuits may be expected to receive.”) and stop converting the output voltage provided by the battery in response to that the output circuit of the control device outputs the stopping voltage (col. 8, ll. 50–55: “… a boost regulator 26' … can be provided at the output of power multiplexer 30 to … regulate main power voltage to that voltage expected by the hibernatable circuits.”); wherein,
as to claim 12, the DC conversion element is a boost converter (boost regulator 26).
It would have been obvious for a PHOSITA to incorporate COOK's DC conversion and monitoring elements into OGAWA’s control device framework, wherein the control device generates the battery signal based on the battery usage signal and the power signal based on a power input signal, to selectively switch battery power on and off and reduce power consumption during periods when external main power is unavailable.
Conclusion
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/D. JOHANN DJANAL-MANN/Examiner, Art Unit 2859
/NATHANIEL R PELTON/Primary Examiner, Art Unit 2859
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