DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Summary of the current invention
The invention describes an auto-zero amplifier circuit in which a null amplifier is continuously connected to a capacitor at its output terminal, eliminating switching-induced noise and improving offset-voltage correction accuracy. This configuration prevents sudden load changes of the null amplifier during phase-switching between the auto-zero and amplifier modes, thereby maintaining stable operation and reducing noise and offset drift in high-precision or minute-signal circuits. The invention can also serve as a highly accurate driver circuit, such as for motor feedback control, using the same low-offset amplification principle.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fasching (US 4,680,585).
Regarding claims 1 and 11, Fasching discloses an amplifier circuit (23) shown in Figure 2 and described in Column 2, line 60 through Column 3, line 51.
(a) "a main amplifier"
Fasching discloses operational amplifier 43 as the main amplifier. See Figure 2, reference numeral 43.
Fasching states: "Amplifier 43 is a commercially available operational amplifier, such as the Model 504 supplied by Burr-Brown, Tucson, Ariz., which has separate inputs 1 and 8 for the application of positive and negative offset voltages, respectively, to null the amplifier output, i.e., zeroing the output of the amplifier." (Col. 3, lines 1-5)
The main amplifier 43 receives the bridge output signal through resistors 41 and 45 and amplifies it with a gain typically set at 1,000. (Col. 2, lines 60-63; Col. 3, lines 7-9)
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Fig. 2 of Fasching annotated by the examiner for ease of reference.
(b) "a null amplifier"
Fasching discloses CMOS operational amplifier 53 as the null amplifier. See Figure 2, reference numeral 53.
Fasching states: "The output of amplifier 43 is connected through a resistor 49 and a VMOS bilateral relay 51 to the inverting input of a CMOS operational amplifier 53 which has the noninverting input thereof connected to ground potential." (Col. 3, lines 16-19)
The function of amplifier 53 is to generate a nulling/correction voltage to compensate for offset in the main amplifier 43, making it a "null amplifier" as claimed. Fasching explains: "Capacitor 57 is charged in a direction and an amount that drives the output of amplifier 43 toward zero volts due to the action of the amplifier 53." (Col. 3, lines 39-41)
(c) Capacitor Connected Without Intervening Switch
Fasching discloses storage capacitor 57 connected directly to the output terminal of null amplifier 53. See Figure 2, reference numeral 57.
Fasching states: "A storage capacitor 57 is connected between the output of amplifier 53 and the inverting input thereof." (Col. 3, lines 23-25)
CRITICAL: There is NO switch interposed between the output terminal of amplifier 53 and capacitor 57. The capacitor 57 is connected directly in a feedback configuration from the output of amplifier 53 to its inverting input, with no intervening switch.
The relay 51 in the circuit is NOT interposed between the output terminal of amplifier 53 and capacitor 57. Rather, relay 51 is located upstream between the output of main amplifier 43 and the input of null amplifier 53. (Col. 3, lines 16-21).
Regarding claim 2, Fasching also teaches
(a) First Operation Mode - Offset Correction
Fasching discloses that the circuit operates in an auto-zero mode where offsets are corrected. During this first operation mode, the null amplifier 53 itself is stabilized.
Fasching describes the auto-zero sequence: "Prior to each pulsed excitation of the bridge 5, the amplifier 43 is excited just prior to the generation of the auto zero strobe pulse, as shown in the timing diagram of FIG. 5. The 2 milliseconds auto zero strobe pulse activates relay 51 thereby connecting the output of amplifier 43 to one side of the storage capacitor 57." (Col. 3, lines 34-39)
(b) Second Operation Mode - Amplification with Offset Correction
Fasching discloses a second operation mode during which the bridge signal is amplified while the offset correction is maintained.
Fasching states: "Thus, the conduction level of transistor 61 is controlled by the charge developed on capacitor 57 and this level is held during the period that the bridge is strobed on and the sample-and-hold circuit 25 is activated to update the channel output and eliminates dc offset error from the output signal." (Col. 3, lines 48-52)
(c) High-Impedance Period During Mode Switching
Fasching discloses VMOS bilateral relay 51 which switches between the operation modes. See Figure 2, reference numeral 51.
When relay 51 opens (deactivates), it enters a high-impedance state, effectively disconnecting the output of main amplifier 43 from the input of null amplifier 53. This is the inherent characteristic of a VMOS relay when in the open state—it presents a high impedance. The relay 51 is controlled by the auto zero strobe pulse (AZS). (Col. 3, lines 19-21) When the auto zero strobe pulse ends, the relay transitions to its open (high-impedance) state, providing a high-impedance period during the transition between operation modes.
Regarding claim 3, Fasching discloses that capacitor 57 must be sized to allow the integrator formed by amplifier 53 and capacitor 57 to properly charge during the 2 milliseconds auto zero strobe period and maintain that charge. The switching frequency is disclosed as 2-10 pulses per second (0.1 Hz to 0.5 Hz). (Col. 4, lines 40-42) For the integrator circuit to function properly at this switching frequency, the capacitor value must be set such that the null amplifier has gain at the switching frequency.
Since Claim 4 combines the features of claims 2 and 3. For the same reasons stated above, Fasching anticipates claim 4.
Claim 5 (dependent from claim 1) adds a mathematical relationship "fm < gm/{2π (C3 + C1)}" where fm is the switching frequency, gm is the transconductance of the null amplifier, and C1 and C3 are capacitances.
For Fasching's circuit to function as disclosed, the relationship between the switching frequency, transconductance, and capacitances must allow proper operation. The fact that Fasching's circuit successfully performs auto-zeroing inherently means that the switching frequency is below the cutoff frequency determined by the transconductance and capacitances, which is what the claimed formula expresses.
Claim 6 (dependent from claim 3) adds that the capacitor value is set to provide a predetermined phase margin. Fasching's circuit must have adequate phase margin to operate stably. The selection of capacitor 57 inherently provides the necessary phase margin for stable operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Fasching in view of Aritsugu (JP 2024048901 A).
Claim 7 recites a driver circuit comprising the amplifier circuit of claim 1 plus "a detector configured to detect a drive current flowing through a motor acting as an external load... or a voltage applied to the motor."
While Fasching does not explicitly disclose a motor as the load, Fasching discloses strain gauge bridges 5-11 as transducers that detect mechanical loading (torque, bending, and axial forces) on the stirrer shaft. (Col. 2, lines 22-31)
The strain gauge bridges function as detectors that detect mechanical stress/strain, which is analogous to detecting drive current or voltage in a motor drive application. Moreover, Fasching states that "the system could be used for various other types of transducers." (Col. 2, lines 33-34), which would include current or voltage sensors for motor control applications.
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Fig. 2 of ARITSUGU reproduced for ease of reference.
Aritsugu uses a precision sensor amplifier circuit in Fig. 2, capable of outputting a sensor signal without intermission while realizing offset compensation using a technology regarding an auto zero circuit. Sensor system 10, a sensor amplifier circuit 100 for amplifying an output signal from a sensor circuit 50 includes an operational amplifier 181 and an offset compensation circuit 110 for reducing an input offset voltage of the operational amplifier. The offset compensation circuit includes a first auto zero circuit 111 and a second auto zero circuit 112 each of which operates in a zero phase for sampling a compensation signal and in an amplification phase for causing the operational amplifier 181 to amplify an output signal in a state that the input offset voltage is cancelled with the compensation signal, and changes over between a first mode in which the first auto zero circuit operates in the amplification phase and the second auto zero operates in the zero phase and a second mode in which the first autozero circuit operates in the zero phase and the second auto zero circuit operates in the amplification phase.
The sensor circuit 50 is used, for example, as an in-vehicle current sensor. When the sensor circuit 50 is used as a device for detecting the current of an inverter or a BMS (Battery Motor System), the sensor circuit 50 is required to have a highly accurate sensing function. However, there is variation in the device characteristics of each sensor circuit 50. To reduce the variation in the device characteristics of the sensor circuit 50, the sensor amplifier circuit 100 has various compensation functions in addition to the offset compensation circuit 110.
To the extent that claim 7 requires specific motor control functionality not explicitly disclosed in Fasching, it have been obvious to a person of ordinary skill in the art with a general knowledge of motor control systems, wherein sensors provide feedback signals to amplifier circuits for closed-loop control for precision control under naturally variable operating conditions, Fasching autozero amplifier would find an ideal application as the amplifier 100 of Aritsugu, because of the precision offset control without a switching noise.
Claims 8-12 depend on claim 7 and add various features already addressed in claims 2-6. For the same reasons set forth above, Fasching’s circuit of Fig. 2 renders claims 8-12 obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.