DETAILED ACTION
Claims 1-17 and 19-21 are pending.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/5/2025 has been entered.
The office acknowledges the following papers:
Claims and remarks filed on 11/7/2025.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fleischer et al. (U.S. 2021/0049230), in view of Official Notice.
As per claim 13:
Fleischer disclosed a method implemented by an Advanced Reduced Instruction Set Computer Machine (ARM) central processing unit (CPU), comprising:
reading, from a first vector register file bank and a second vector register file bank, a first source vector (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, 19-22, and 28-29)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. Vectors of matrix A are read out for multiple iterations of matrix multiply and accumulate operations.);
reading, from the first vector register file bank and the second vector register file bank, a second source vector in parallel to the first source vector (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, 19-22, and 28-29)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. Vectors of matrix B are read out for multiple iterations of matrix multiply and accumulate operations, at the same time vectors of matrix A are read out for an iteration.);
computing, using an outer product engine that is an array of adders and multipliers, an outer product of the first source vector and the second source vector using temporal SIMD (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, and 19-22)(Fleischer disclosed rows and columns of MAC circuits (i.e. outer product engine) to multiply and accumulate two source matrices to generate an outer product of the matrices (i.e. multiply row of first matrix by column of second matrix). “Temporal SIMD refers to executing a single instruction over multiple data in the time domain” (specification paragraph 15). The matrix instruction is executed over multiple iterations based on the matrix size. In the example shown in figure 1, the matrix operation (i.e. single instruction) is performed over 8 iterations (i.e. temporal) using the input matrices and intermediate results (i.e. multiple data).); and
storing, in an accumulator array, the outer product (Fleischer: Figure 1 element 130, paragraphs 15-17)(Fleischer disclosed an accumulator register (i.e. accumulator array) storing the intermediate and final product of the matrix MAC operation.), wherein a size of the segments of the first source vector and a size of the segments of the second source vector is selected based on a size of the accumulator array and a target bandwidth of a connection to a cache (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. Each portion of the source matrix stored in a given register bank reads upon a segment. Official notice is given that load store units can load 128-bits of data at a time from a data cache to a vector register for the advantage of faster data access speeds. Thus, it would have been obvious to allow for loading vector registers in the combination 128-bits at a time. The size of vector elements sent to the columns and rows of the MAC array is based on the size of the MAC array.) and using temporal SIMD in computing the outer product ensures a size of the outer product remains within the target bandwidth of the connection (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, and 19-22)(Fleischer disclosed a MAC circuit (i.e. outer product engine) to multiply and accumulate two source matrices to generate an outer product of the matrices (i.e. multiply row of first matrix by column of second matrix). “Temporal SIMD refers to executing a single instruction over multiple data in the time domain” (specification paragraph 15). The matrix instruction is executed over multiple iterations based on the matrix size. In the example shown in figure 1, the matrix operation (i.e. single instruction) is performed over 8 iterations (i.e. temporal) using the input matrices and intermediate results (i.e. multiple data). The final product is stored within 8 128-bit vector registers. In view of the above official notice, the load store unit loads 128-bits of data at a time from the cache to the vector registers (i.e. target bandwidth of a connection to a cache). Thus, the final product is stored in 8 vector registers comprising 128-bits (i.e. target bandwidth of the connection.).).
As per claim 14:
Fleischer disclosed the method of claim 13, wherein reading from the first vector register file bank and the second vector register file bank the first source vector further includes reading the first source vector in segments over a plurality of clock cycles, and wherein reading from the first vector register file bank and the second vector register file bank the second source vector further includes reading the second source vector in segments over the plurality of clock cycles (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, 19-22, 26, and 29)(Fleischer disclosed a MAC circuit to multiply and accumulate two source matrices to generate an outer product of the matrices. Each portion of the source matrix stored in a given register bank reads upon a segment. This is performed over eight iterations (using the 8x8 matrices in the figures) using vector source matrices’ input data over multiple cycles.).
As per claim 15:
Fleischer disclosed the method of claim 14, wherein the outer product is stored in stages in an accumulator array (Fleischer: Figure 1 element 130, paragraphs 15-17)(Fleischer disclosed an accumulator register (i.e. accumulator array) storing the intermediate and final product of the matrix MAC operation.) and the stages are provided to a cache from the accumulator array (Fleischer: Figure 1 elements 110 and 120-122, paragraphs 12, 14-15, 17, and 19-22)(An embodiment allows for the accumulation registers to be stored within the source vector register file banks. Official notice is given that load store units can be used to transfer data between register files and data caches for the advantage of faster data access speeds. Thus, it would have been obvious to one of ordinary skill in the art to implement a load store unit and data cache in Fleischer for moving data between registers and memory.).
As per claim 16:
Fleischer disclosed the method of claim 14, wherein computing the outer product further includes:
computing a first outer product of a first segment of the first source vector and a first segment of the second source vector over a first clock cycle and storing the first outer product in the accumulator array (Fleischer: Figures 1 and 4 elements 120-122, 130, 402-404, paragraphs 12, 14, 17, 19-22, and 26, 29-30, and 33-34)(Fleischer disclosed a MAC circuit to multiply and accumulate two source matrices to generate an outer product of the matrices (i.e. multiply row of first matrix by column of second matrix). Each portion of the source matrix stored in a given register bank reads upon a segment. A first outer product is calculated during a first iteration occurring during a first clock cycle.);
continuing to compute outer products of the first segment of the first source vector with subsequent segments of the second source vector over subsequent clock cycles until the outer product is computed for the first segment of the first source vector (Fleischer: Figures 1 and 4 elements 120-122, 130, 402-404, paragraphs 12, 14, 17, 19-22, and 26, 29-30, and 33-34)(Fleischer disclosed a MAC circuit to multiply and accumulate two source matrices to generate an outer product of the matrices (i.e. multiply row of first matrix by column of second matrix). Each portion of the source matrix stored in a given register bank reads upon a segment. Subsequent outer products are calculated during subsequent iterations occurring during subsequent clock cycles.);
continuing to compute outer products of subsequent segments of the first source vector and subsequent segments of the second source vector over subsequent clock cycles until the outer product is computed for all pairs in a Cartesian product of the segments of the first source vector and the second source vector (Fleischer: Figures 1 and 4 elements 120-122, 130, 402-404, paragraphs 12, 14, 17, 19-22, and 26, 29-30, and 33-34)(Fleischer disclosed a MAC circuit to multiply and accumulate two source matrices to generate an outer product of the matrices (i.e. multiply row of first matrix by column of second matrix). Each portion of the source matrix stored in a given register bank reads upon a segment. Subsequent outer products are calculated during subsequent iterations occurring during subsequent clock cycles. A cartesian product is generated after all iterations are computed and accumulated.).
As per claim 17:
Fleischer disclosed the method of claim 14, wherein a size of the segments is selected so a required bandwidth meets a target that is less than or equal to a maximum bandwidth supported by a connection to a cache (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. Official notice is given that load store units can load 128-bits of data at a time from a data cache to a vector register for the advantage of faster data access speeds. Thus, it would have been obvious to allow for loading vector registers in the combination 128-bits at a time.).
As per claim 19:
Fleischer disclosed the method of claim 14, wherein a size of the first vector register file bank and a size of the second vector register file bank is equal to a target bandwidth of a connection to a cache or less than a target bandwidth of a connection to the cache (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. Official notice is given that the load store unit can load 128-bits of data at a time from a data cache to a vector register for the advantage of faster data access speeds. Thus, it would have been obvious to allow for loading vector registers in the combination 128-bits at a time.).
As per claim 20:
Fleischer disclosed the method of claim 13, wherein a target bandwidth of a connection to a cache is 128 bits (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. Official notice is given that load store units can load 128-bits of data at a time from a data cache to a vector register for the advantage of faster data access speeds. Thus, it would have been obvious to allow for loading vector registers in the combination 128-bits at a time.), a size of an outer product array is 256 bits (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, 25, and 28)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. The output matrix can be stored within 8 128-bit vector registers. Official notice is given that convolution operations can accumulate over moving windows of destination data for the advantage of reducing output data (e.g. final products a11+a12+a21+a22 is stored in a11. Thus, it would have been obvious to one of ordinary skill in the art to perform further accumulations on final products to reduce the destination vector from 1024-bits to 256-bits.), a size of the first source vector is 1024 bits, a size of the second source vector is 1024 bits, a size of the first vector register file bank is 128 bits, and a size of the second vector register file bank is 128 bits (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. Both source matrices can be stored within the 8 register banks storing 128-bit vector registers.).
Claims 1-12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Randall et al. (U.S. 2024/0403050), Fleischer et al. (U.S. 2021/0049230), in view of Official Notice.
As per claim 1:
Randall and Fleischer disclosed an Advanced Reduced Instruction Set Computer Machine (ARM) central processing unit (CPU), comprising:
a layer 1 cache (Randall: Figure 22 elements 2214 and 2222, paragraph 122)(Official notice is given that LSUs can load/store data from/to a L1 data cache for the advantage of faster memory access speeds. Thus, it would have been obvious to one of ordinary skill in the art to implement an on-chip L1 data cache coupled to the LSU.);
a load store unit configured to load data into a vector register file (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. The combination implements the vector register file banks of Fleischer into the processor of Randall.), wherein the load store unit is in communication with the layer 1 cache (Randall: Figure 22 elements 2214 and 2222, paragraph 122)(In view of the above official notice, the LSUs load/store data from/to a L1 data cache.);
an arithmetic unit configured to perform an operation on the data from the vector register file (Randall: Figures and 22 elements 2211 and 2220, paragraphs 33, 36, 45, 77, 81, 86, and 121-124)(The SVE execution unit executes various vector operations using the vector register file data.); and
an outer product engine that is an array of adders and multipliers configured to implement an ARM scalable matrix extensions (SME) instruction set by performing an outer product of the data (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, and 19-22)(Randall: Figure 22 element 2213, paragraph 121)(Fleischer disclosed columns and rows of MAC circuits (i.e. outer product engine array) to multiply and accumulate two source matrices to generate an outer product of the matrices (i.e. multiply row of first matrix by column of second matrix). The combination implements the MAC circuit of Fleischer within the SME circuitry of Randall.), wherein the outer product engine is in communication with the vector register file and the load store unit (Fleischer: Figure 1 elements 110 and 120-122, paragraphs 12, 14-15, 17, and 19-22)(Randall: Figure 22 element 2213, 2220, and 2222, paragraphs 121-122)(The combination implements the MAC circuit of Fleischer within the SME circuitry of Randall. The combination implements the vector register file banks of Fleisher into the processor of Randall. This allows for direct communication with the vector register files and indirect communication with the LSU.) and the outer product engine further includes an accumulator array that stores the outer product of the data generated by the outer product engine (Fleischer: Figure 1 element 130, paragraphs 15-17)(Randall: Figure 22 element 2220, paragraph 122)(Fleischer disclosed an accumulator register (i.e. accumulator array) storing the intermediate and final product of the matrix MAC operation. The combination implements the accumulator register separate from the register file of Randall. Additionally, an embodiment allows for the accumulation registers to be stored within the source vector register file banks.).
The advantage of performing matrix multiply and accumulate operations using vector registers and multiplication arrays is that large amounts of products can be calculated in parallel for increased performance. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the MAC circuitry of Fleischer within the SME circuitry of Randall for the above advantage.
As per claim 2:
Randall and Fleischer disclosed the ARM CPU of claim 1, further comprising:
a first multiplexer used by the vector register file to read the data from the outer product engine or the load store unit (Randall: Figure 22 elements 2211, 2213, and 2220, paragraphs 121-122)(Official notice is given that multiplexers can be used to select between multiple execution unit outputs for the advantage of reducing register file write port costs. Thus, it would have been obvious to one of ordinary skill in the art to implement a multiplexer in Randall to select between writing execution results to the register file from the SVE and SME execution units.); and
a second multiplexer used by the load store unit to read the data from the outer product engine or the vector register file (Randall: Figure 22 elements 2211, 2213, and 2220-2222, paragraphs 121-122)(Official notice is given that execution units can process fused operations that perform an operation and write to memory for the advantage of increased performance and reduced program sizes. Official notice is given that multiplexers can be used to select between multiple processing unit outputs (e.g. VRF, execution unit, etc.) for the advantage of reducing data cache write port costs. Thus, it would have been obvious to one of ordinary skill in the art to implement a multiplexer in Randall to select between writing execution results or data from the register file to a data cache.).
As per claim 3:
Randall and Fleischer disclosed the ARM CPU of claim 1, wherein an output of the accumulator array is available to the vector register file and the load store unit (Fleischer: Figure 1 element 130, paragraphs 15-17)(Randall: Figure 22 element 2220, paragraph 122)(The combination implements the accumulator register within the register file of Randall. This allows for the final product value to be available to the vector register file and LSU.).
As per claim 4:
Randall and Fleischer disclosed the ARM CPU of claim 1, wherein the vector register file uses temporal SIMD to provide the data to the outer product engine for performing the outer product of the data over a plurality of cycles (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, 19-22, 26, and 29)(Randall: Figure 22 element 2213, paragraph 121)(The broadest reasonable interpretation of temporal SIMD is based on paragraph 16, which states it refers to “executing a single instruction over multiple data in the time domain.” Fleischer disclosed a MAC circuit (i.e. outer product engine) to multiply and accumulate two source matrices to generate an outer product of the matrices. This is performed over eight iterations (using the 8x8 matrices in the figures) using vector input data over multiple cycles (i.e. temporal SIMD). The combination implements the MAC circuit of Fleischer within the SME circuitry of Randall.).
As per claim 5:
Randall and Fleischer disclosed the ARM CPU of claim 4, wherein the temporal SIMD maintains a size of the data within a bandwidth requirement for a connection to the layer 1 cache (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. The combination implements the vector register file banks of Fleischer into the processor of Randall. Official notice is given that the load store unit can load 128-bits of data at a time from a data cache to a vector register for the advantage of faster data access speeds. Thus, it would have been obvious to allow for loading vector registers in the combination 128-bits at a time.).
As per claim 6:
Randall and Fleischer disclosed the ARM CPU of claim 4, wherein the outer product engine computes the outer product of the data in stages (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, 19-22, 26, and 29)(Randall: Figure 22 element 2213, paragraph 121)(The combination implements the MAC circuit of Fleischer within the SME circuitry of Randall. Fleischer disclosed a MAC circuit (i.e. outer product engine) to multiply and accumulate two source matrices to generate an outer product of the matrices. This is performed over eight iterations (using the 8x8 matrices in the figures) using vector input data over multiple cycles (i.e. temporal SIMD).) and an accumulator array stores the stages of the outer product (Fleischer: Figure 1 element 130, paragraphs 15-17)(Randall: Figure 22 element 2220, paragraph 122)(Fleischer disclosed an accumulator register (i.e. accumulator array) storing the intermediate and final product of the matrix MAC operation. The combination implements the accumulator register within the register file of Randall.).
As per claim 7:
Randall and Fleischer disclosed the ARM CPU of claim 1, wherein the vector register file includes a plurality of vector register file banks (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. The combination implements the vector register file banks of Fleischer into the processor of Randall.) and the data from the plurality of vector register file banks is read out in parallel to the outer product engine over a plurality of cycles (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, 19-22, 26, and 29)(Randall: Figure 22 element 2213, paragraph 121)(Fleischer disclosed a MAC circuit (i.e. outer product engine) to multiply and accumulate two source matrices to generate an outer product of the matrices. This is performed over eight iterations (using the 8x8 matrices in the figures) using vector input data over multiple cycles (i.e. temporal SIMD). The combination implements the MAC circuit of Fleischer within the SME circuitry of Randall.).
As per claim 8:
Randall and Fleischer disclosed the ARM CPU of claim 7, wherein the plurality of vector register file banks equals two vector register file banks (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. The combination implements the accumulator register within the register file of Randall. It would have been obvious to one of ordinary skill in the art that a smaller number of register banks can be used for larger data element sizes (i.e. 32 bits) or for storing smaller size source matrices. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.), and each register file bank stores segments of both source vectors used in the outer product (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. Each portion of the source matrix stored in a given register bank reads upon a segment. The combination implements the vector register file banks of Fleischer into the processor of Randall.).
As per claim 9:
Randall and Fleischer disclosed the ARM CPU of claim 8, wherein each source vector is stored in segments within the plurality of vector register file banks (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. The combination implements the vector register file banks of Fleischer into the processor of Randall.) and the segments are read out in parallel over the plurality of cycles (Fleischer: Figure 1 element 120-122, paragraphs 12, 14, 17, 19-22, 26, and 29)(Randall: Figure 22 element 2213, paragraph 121)(Fleischer disclosed a MAC circuit (i.e. outer product engine) to multiply and accumulate two source matrices to generate an outer product of the matrices. This is performed over eight iterations (using the 8x8 matrices in the figures) using vector input data over multiple cycles (i.e. temporal SIMD). The combination implements the MAC circuit of Fleischer within the SME circuitry of Randall.).
As per claim 10:
Randall and Fleischer disclosed the ARM CPU of claim 9, wherein a size of each source vector is 1024 bits and a number of segments of each source vector is four (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. The combination implements the accumulator register within the register file of Randall. It would have been obvious to one of ordinary skill in the art that a smaller number of register banks can be used for larger data element sizes (i.e. 32 bits). In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.).
As per claim 11:
Randall and Fleischer disclosed the ARM CPU of claim 7, wherein a size of the plurality of vector register file banks is 128 bits (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, 25, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. A matrix can be stored within 8 128-bit vector registers. The combination implements the accumulator register within the register file of Randall.).
As per claim 12:
Randall and Fleischer disclosed the ARM CPU of claim 7, wherein a size of an accumulator array used by the outer product engine to store the outer product is 256 bits (Fleischer: Figures 1-3 element 110, paragraphs 14, 16, 25, and 28)(Randall: Figure 22 elements 2220 and 2222, paragraph 122)(Fleischer disclosed vector register file banks for storing source matrices for matrix multiply and accumulate operations. The output matrix can be stored within 8 128-bit vector registers. The combination implements the accumulator register within the register file of Randall. Official notice is given that convolution operations can accumulate over moving windows of destination data for the advantage of reducing output data (e.g. final products a11+a12+a21+a22 is stored in a11. Thus, it would have been obvious to one of ordinary skill in the art to perform further accumulations on final products to reduce the destination vector from 1024-bits to 256-bits.).
As per claim 21:
Randall and Fleischer disclosed the ARM CPU of claim 1, further comprising:
a first multiplexer that selects to read the data for the vector register file from the arithmetic unit or an output of the outer product engine (Randall: Figure 22 elements 2211, 2213, and 2220, paragraphs 121-122)(Official notice is given that multiplexers can be used to select between multiple execution unit outputs for the advantage of reducing register file write port costs. Thus, it would have been obvious to one of ordinary skill in the art to implement a multiplexer in Randall to select between writing execution results to the register file from the SVE and SME execution units.), wherein the data from the vector register file moves between the vector register file, output product engine, and the accumulator array (Fleischer: Figure 1 element 130, paragraphs 15-17)(Randall: Figure 22 element 2220, paragraph 122)(Fleischer disclosed an accumulator register (i.e. accumulator array) storing the intermediate and final product of the matrix MAC operation. The combination implements the accumulator register separate from the register file of Randall. Additionally, an embodiment allows for the accumulation registers to be stored within the source vector register file banks. This allows for data to move between the vector register file, multiplier circuitry, and accumulation registers.); and
a second multiplexer that selects to read the data for the load store unit from the accumulator array in from the outer product engine or the vector register file (Randall: Figure 22 elements 2211, 2213, and 2220-2222, paragraphs 121-122)(Official notice is given that execution units can process fused operations that perform an operation and write to memory for the advantage of increased performance and reduced program sizes. Official notice is given that multiplexers can be used to select between multiple processing unit outputs (e.g. VRF, execution unit, etc.) for the advantage of reducing data cache write port costs. Thus, it would have been obvious to one of ordinary skill in the art to implement a multiplexer in Randall to select between writing execution results or data from the register file to a data cache.).
Response to Arguments
The arguments presented by Applicant in the response, received on 11/7/2025 are partially considered persuasive.
Applicant argues regarding claim 1:
“The cited reference Randall is filed on November 14, 2023, which was after the filing date (October 5, 2023) of this application. The cited reference Randall is a continuation-in-part of U.S. Application No. 18/329,456, filed on June 5, 2023 (the parent application). However, the features recited in the Office Action on pages 9 and 10 from Randall used in rejecting independent claim 1 are not present in the parent application. For example, the Office Action cites to Fig. 22 element 2213 on pages 9 and 10 of the Office Action. The Office Action states on page 18 that the parent application "is missing the SVE and SME boxes in the processing circuitry" of Randall and cites to paragraph 40 of the parent application on page 18 for providing support for these features. Applicant respectfully disagrees.
Paragraph [0040] of the parent application discloses "generally, a merge-sort operation similar to merge-sort operation 600 may be implemented without the help of IDXMOV operations. For example, the four IDXMOV operations mentioned above in connection with example merge-sort operation 600 may be replaced with two scatter store operations that would result in sixteen micro-operations for a 512-bit scalable matrix extension (SME) and/or for streaming scalable vector extension (SVE) having 64-bit keys." Applicant respectfully submits that paragraph [0040] discuses changes to a merge-sort operation and does not provide support for the SVE and SME boxes in the processing circuity in Fig. 22 of Randall. For at least the above reasons, Applicant maintains that Randall is not a proper prior art reference for the features recited on pages 9 and 10 of the Office Action.”
This argument is partially found to be persuasive for the following reason. The applicant is correct that the CIP application number 18/329,456 with the prior art date of June 5, 2023 doesn’t have the exact same figure 22 of the cited reference in the rejection. The CIP application is missing the SVE and SME boxes in the processing circuitry. The rejection cited SME circuitry element 2213 of Randall within the rejection. The CIP application in paragraph 40 cites SME operations in conjunction with IDXMOV operations. The citation still discusses 512-bit scalable matrix extension and streaming scalable vector extension operations. In both instances, these elements are both considered “processing circuitry”. Thus, the prior art CIP application has support for SME processing circuitry that is used in the rejection, including both the CIP SME operations and the matrix multiplication operations of Fleisher.
Applicant argues for claim 1:
“The cited portions of Fleischer disclose that "the circuit 120 can be a multiplier circuit operable to perform multiplication between data arrays or matrices. For example, the circuit 120 can be operable to multiply matrices A and B to produce a data array C, where the data array C can be represented by a (nxp) matrix including n rows and p columns. To be described in more detail below, the circuit 120 can multiply portions of matrices A and B to generate portions of C and store the portions of C in the register file 130, where the multiplication of the portions can be performed in parallel. The circuit 120 can be further operable to sum or accumulate the portions of C stored in the register file 130 to produce the matrix C." See, Fleischer, paragraph [0015].
Applicant submits that the cited portions of Fleischer do not disclose or suggest at least an outer product engine that is an array of adders and multipliers configured to implement an ARM scalable matrix extensions (SME) instruction set by performing an outer product of the data, wherein the outer product engine is in communication with the vector register file and the load store unit and the outer product engine includes an accumulator array that stores the outer product of the data generated by the outer product engine," as recited in amended independent claim 1.
Instead, the cited portions of Fleischer disclose that "the circuit 120 can be a multiplier circuit operable to perform multiplication between data arrays or matrices . . . [and] the circuit 120 can be further operable to sum or accumulate the portions of C stored in the register file 130 to produce the matrix C."”
This argument is not found to be persuasive for the following reason. The multiplier circuitry is an array of multipliers and adders that perform the matrix multiply and accumulation processing. The circuitry shows individual MAC elements within rows and columns of the circuitry that multiply A and B vector elements, as well as accumulate the product with the received C element. The combination implements the multiplier circuitry within Randall for performing SME instructions. Thus, reading upon the claimed limitations.
Applicant argues for claim 13:
“Applicant also submits that there is no disclosure in Fleischer of at least "wherein a size of the segments of the first source vector and a size of the segments of the second source vector is selected based on a size of the accumulator array and a target bandwidth of a connection to a cache and using temporal SIMD in computing the outer product ensures a size of the outer product remains within the target bandwidth of the connection," as recited in amended independent claim 13.”
This argument is not found to be persuasive for the following reason. The stored vector elements of the register file are sized based on the size of the matrix multiplier circuitry. The official notice taken allows for the register sizes to also be based on the bandwidth available for loading them from the data cache. Thus, reading upon the claimed limitations.
Applicant argues regarding the official notice:
“The Applicant respectfully requests that the Examiner provide references supporting the teachings officially noticed, as well as provide the required motivation or suggestion to combine reference with the other art of record.”
This argument is not found to be persuasive for the following reason. MPEP 2144.03 C states “To adequately traverse such a finding, an applicant must specifically point out the supposed errors in the examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art … A general allegation that the claims define a patentable invention without any reference to the examiner’s assertion of official notice would be inadequate.” Applicant’s response hasn’t included why the noticed fact isn’t considered well-known in the art. Thus, the official notices taken are maintained.
In this instance, data bus bandwidths between a data cache and a register file are very well-known, including data bus bandwidths of 128-bits.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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