DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 22 January 2024, 20 December 2024 and 14 July 2025 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2, 17 and 24 are objected to because of the following informalities:
In claim 2, line 2 and claim 17, line 3: “radius between 0,5 mm and 5 mm.” should read: -- radius between 0.5 mm and 5 mm.--
In claim 24, lines 3 and 6: “of the substrate represents a structured deposition” should read:
-- of the substrate configured a structured deposition --
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 7, 9, 14-16, 18-19, 22, 24-25 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moscicki (Moscicki et. al., Interconnection Process by Ink Jet Printing Method, 12th IEEE International Conference on Nanotechnology, Aug. 2012).
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Annotated Fig. 8, Moscicki.
Regarding claim 1, Moscicki teaches, a method (interconnection process made by ink-jet printing, Title, Abstract, Figs. 1 to 8), comprising
providing an electrically insulating substrate (polyimide substrate, see annotated Fig. 8);
forming a through-hole (drill holes in the polyimide…four different microvias hole diameters were drilled, page 2, col. 1, holes with diameter from 30 to 60 µm were drilled by laser beam in the polyimide substrates, Abstract) in the substrate between a first and a second main surface region of the substrate (see Fig. 8);
structured deposition of conductive material (conductive structures in form of square of dimensions 2.5 x 2.5 cm2 were initially printed on one side of substrate over the area with drilled holes array, page 2, col. 2) on the first main surface region of the substrate, so that walls of the through-hole are covered by the conductive material (microvias were filled i.e. both sides of flexible substrate were connected through the whole holes, page 3, col. 1, see Figs. 2-3 and 8) and so that first conductive traces are formed on the first main surface region of the substrate (conductive structures in form of square of dimensions 2.5 x 2.5 cm2, see Fig. 8 and the Note below); and
structured deposition of further conductive material (then the structures were printed on the other side and the whole samples were dried and sintered, page 2, col. 2) on the second main surface region of the substrate so that second conductive traces are formed on the second main surface region of the substrate (conductive structures in form of square of dimensions 2.5 x 2.5 cm2, page 2, col. 2).
Note: Moscicki teaches inkjet printing conductive material in form of conductive structures, in which the inkjet printing anticipates “structured deposition of conductive material”, “first conductive traces” and “second conductive traces” as recited in claim 1. If applicant disagrees, see the disclosed claim 9.
Regarding claim 16, Moscicki teaches, a method comprising
providing an electrically insulating substrate (polyimide substrate, see annotated Fig. 8);
forming a through-hole in the substrate between a first and a second main surface region of the substrate (drill holes in the polyimide…four different microvias hole diameters were drilled, page 2, col. 1, holes with diameter from 30 to 60 µm were drilled by laser beam in the polyimide substrates, Abstract);
depositing conductive material on the first main surface region of the substrate, so that walls of the through-hole are covered by the conductive material (conductive structures in form of square of dimensions 2.5 x 2.5 cm2 were initially printed on one side of substrate over the area with drilled holes array, page 2, col. 2, microvias were filled i.e. both sides of flexible substrate were connected through the whole holes, page 3, col. 1, see Figs. 2-3 and 8); and
depositing further conductive material on the second main surface region of the substrate (then the structures were printed on the other side and the whole samples were dried and sintered, page 2, col. 2).
Regarding claims 3 and 18, Moscicki teaches the recited limitations with respect to claims 1 and 16. Moscicki further teaches, wherein the structured deposition of the conductive material on the first main surface region of the substrate is performed so that the first conductive traces comprise a thickness between 20 nm and 1 µm and wherein the structured deposition of the further conductive material on the second main surface region of the substrate is performed so that the second conductive traces comprise a thickness between 20 nm and 1 µm (printed plane structures has a small thickness - about 0.4 µm, page 2, col. 2).
Regarding claims 4 and 19, Moscicki teaches the recited limitations with respect to claims 1 and 16. Moscicki further teaches, wherein the through-hole is formed by cold laser ablation (holes with diameter from 30 to 60 µm were drilled by laser beam in the polyimide substrates, Abstract).
Regarding claims 7 and 22, Moscicki teaches the recited limitations with respect to claims 1 and 16. Moscicki further teaches, wherein the method comprises cleaning the substrate with the through-hole (after drilling both surface of substrate were cleaned, by rinsing successively in acetone, page 2, col. 2) before the structured deposition of the conductive material on the first main surface region of the substrate and the structured deposition of the further conductive material on the second main surface region of the substrate.
Regarding claim 9, Moscicki teaches the recited limitations with respect to claim 1. Moscicki further teaches, the method according to claim 1, wherein the structured deposition of the conductive material on the first main surface region of the substrate is performed by printing using the through-hole in the substrate as reference for alignment of the first conductive traces (conductive structures in form of square of dimensions 2.5 x 2.5 cm2 were initially printed on one side of substrate over the area with drilled holes array, page 2, col. 2, unless otherwise defined, inkjet printing anticipates the recited limitation, “performed by printing using the through-hole in the substrate as reference for alignment” ); and/or
the structured deposition of the further conductive material on the second main surface region of the substrate is performed by printing (then the structures were printed on the other side and the whole samples were dried and sintered, page 2, col. 2) using the through-hole in the substrate as reference for alignment of the second conductive traces.
Regarding claim 14, Moscicki teaches the recited limitations with respect to claim 1. Moscicki further teaches, the method according to claim 1, wherein two or more through-holes are formed (see microvias in Fig. 8) in the substrate between the first and the second main surface region of the substrate at the forming of the through-hole; and wherein the structured deposition of conductive material on the first main surface region of the substrate is performed, so that walls of the two or more through-holes are covered by the conductive material (see Fig. 8).
Regarding claim 15, Moscicki teaches the recited limitations with respect to claim 1. Moscicki further teaches, a sheet for double sided electronics (see Fig. 8), manufactured by the method of claim 1, comprising a non-conducting substrate (polyimide substrate) with a through-hole electrically connecting first conductive traces on a first main surface region of the substrate with second conductive traces on a second main surface region of the substrate (see Fig. 8).
Regarding claim 24, Moscicki teaches the recited limitations with respect to claim 16. Moscicki further teaches, the method according to claim 16, wherein the deposition of the conductive material on the first main surface region of the substrate represents a structured deposition (conductive structures in form of square of dimensions 2.5 x 2.5 cm2 were initially printed on one side of substrate, page 2, col. 2 and the Note above), so that first conductive traces are formed on the first main surface region of the substrate; and wherein the deposition of the further conductive material on the second main surface region of the substrate represents a structured deposition (then the structures were printed on the other side and the whole samples were dried and sintered, page 2, col. 2), so that second conductive traces are formed on the second main surface region of the substrate.
Regarding claim 25, Moscicki teaches the recited limitations with respect to claim 24. Moscicki further teaches, the method according to claim 24,
wherein the structured deposition of the conductive material on the first main surface region of the substrate is performed by printing using the through-hole in the substrate as reference for alignment of the first conductive traces (conductive structures in form of square of dimensions 2.5 x 2.5 cm2 were initially printed on one side of substrate over the area with drilled holes array, page 2, col. 2, unless otherwise defined, inkjet printing anticipates the recited limitation, “performed by printing using the through-hole in the substrate as reference for alignment”); and/or
the structured deposition of the further conductive material on the second main surface region of the substrate is performed by printing using the through-hole in the substrate as reference for alignment of the second conductive traces (then the structures were printed on the other side and the whole samples were dried and sintered, page 2, col. 2).
Regarding claim 29, Moscicki teaches the recited limitations with respect to claim 24. Moscicki further teaches, the method according to claim 24, wherein two or more through-holes are formed (see the microvias in Fig. 8) in the substrate between the first and the second main surface region of the substrate at the forming of the through-hole; and wherein the structured deposition of conductive material on the first main surface region of the substrate is performed, so that walls of the two or more through-holes are covered by the conductive material (see Fig. 8).
Claim(s) 16 and 24 are alternatively, and claim 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choon (KR 20140133464).
Regarding claim 16, Choon teaches, a method comprising
providing an electrically insulating substrate (substrate 10, see annotated Fig. 10 below, substrate 10 used in this step may be a polyimide film (PI), para. [0048]);
forming a through-hole in the substrate between a first and a second main surface region of the substrate (through hole 11, drilling step S810…drilling step (S810) is a step of drilling the substrate (10) to form a through hole (11) that completely penetrates the substrate (10) …drilling step is performed on the substrate through processes widely known in the technical field, such as CNC drilling, UV laser, para. [0171-0172]);
depositing conductive material on the first main surface region of the substrate, so that walls of the through-hole are covered by the conductive material (see annotated Fig. 10 below, first coating layer forming step S820 may include forming a first coating layer 20 on one surface of the substrate 10 and filling at least a portion of the inside of the through hole 11 formed in the substrate 10 with conductive ink, para. [0174]); and
depositing further conductive material on the second main surface region of the substrate (second coating layer forming step S830 may include forming a second coating layer 30 on the other surface of the substrate 10 and forming the inside of the partially filled through hole 11 in the first coating layer forming step S820, and completely filled with the conductive ink through the opposite opening, para. [0175-0181]).
Regarding claim 24, Choon teaches the recited limitations with respect to claim 16. Chon further teaches, the method according to claim 16, wherein the deposition of the conductive material on the first main surface region of the substrate represents a structured deposition (inkjet printing, para. [0061], see Fig. 10, first coating layer forming step S820 may include forming a first coating layer 20 on one surface of the substrate 10 and filling at least a portion of the inside of the through hole 11 formed in the substrate 10 with conductive ink, para. [0174]), so that first conductive traces are formed on the first main surface region of the substrate; and wherein the deposition of the further conductive material on the second main surface region of the substrate represents a structured deposition (second coating layer forming step S830 may include forming a second coating layer 30 on the other surface of the substrate 10 and forming the inside of the partially filled through hole 11 in the first coating layer forming step S820, and completely filled with the conductive ink through the opposite opening, para. [0175-0181]), so that second conductive traces are formed on the second main surface region of the substrate.
Regarding claim 30, Choon teaches the recited limitations with respect to claim 16. Choon further teaches, the method according to claim 16, wherein the method is part of a sheet-to-sheet-process, a roll-to-sheet-process or a roll-to-roll-process (see para. [0172]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 alternatively, and claims 10, 12-13, 26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Choon (KR 20140133464).
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Annotated Fig. 10 Choon.
Regarding claim 1, Choon teaches, a method, comprising
providing an electrically insulating substrate (substrate 10, Fig. 10, substrate 10 used in this step may be a polyimide film (PI), para. [0048]);
forming a through-hole (through hole 11, drilling step S810…drilling step (S810) is a step of drilling the substrate (10) to form a through hole (11) that completely penetrates the substrate (10)… drilling step is performed on the substrate through processes widely known in the technical field, such as CNC drilling, UV laser, para. [0171-0172]) in the substrate between a first and a second main surface region of the substrate (see Fig. 10);
structured deposition of conductive material (first coating layer 20) on the first main surface region of the substrate, so that walls of the through-hole are covered by the conductive material (see annotated Fig. 10 above, first coating layer forming step S820 may include forming a first coating layer 20 on one surface of the substrate 10 and filling at least a portion of the inside of the through hole 11 formed in the substrate 10 with conductive ink, para. [0174]) and so that first conductive traces are formed on the first main surface region of the substrate (see step S860, circuit pattern forming step (S860) is a step of forming a circuit pattern by patterning the first coating layer (20), the second coating layer (30), para. [0181]); and
structured deposition of further conductive material (second coating layer 30) on the second main surface region of the substrate so that second conductive traces are formed on the second main surface region of the substrate (second coating layer forming step S830 may include forming a second coating layer 30 on the other surface of the substrate 10 and forming the inside of the partially filled through hole 11 in the first coating layer forming step S820, and completely filled with the conductive ink through the opposite opening…circuit pattern of a desired shape is formed by patterning the first coating layer (20), the second coating layer (30), and the plating layer (40) plated thereon through a photolithography process widely known in the technical field, para. [0175-0181]).
From the teachings of Choon in para. [0059-0061], “first coating layer (20) or the second coating layer (30) may be formed by a printing process to form a circuit pattern, and the remaining coating
layer may be formed by a patterning process through a separate circuit pattern formation
step to form a circuit pattern…a printed circuit board can be manufactured by selectively using a direct printing process that forms a circuit pattern simultaneously with coating, such as inkjet printing, or an indirect printing process that patterns a circuit pattern after coating, such as a lithography process, thereby enabling the construction of an efficient process” one of ordinary skill in the art would have known that printing forms a structured deposition, and photolithography and etching process forms conductive traces. Therefore, in view of the teachings of Choon, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of forming a double sided flexible circuit board of Choon and forming a structured printing onto the insulating substrate so that it enables forming circuit patterns through a printing process.
Regarding claims 10 and 26, Choon teaches the recited limitations with respect to claims 1 and 16. Choon further teaches, wherein the structured deposition of the conductive material on the first main surface region of the substrate is performed by depositing the conductive material on the first main surface region of the substrate to cover the entire first main surface region of the substrate with a layer of the conductive material and structuring the layer of the conductive material to form the first conductive traces using the through-hole in the substrate as reference for alignment of the first conductive traces; and/or wherein the structured deposition of the further conductive material on the second main surface region of the substrate is performed by depositing the further conductive material on the second main surface region of the substrate to cover the entire second main surface region of the substrate with a layer of the further conductive material and structuring the layer of the further conductive material to form the second conductive traces using the through-hole in the substrate as reference for alignment of the second conductive traces (either the first coating layer (20) or the second coating layer (30) may be formed by a printing process to form a circuit pattern, and the remaining coating layer may be formed by a patterning process through a separate circuit pattern formation
step to form a circuit pattern…an indirect printing process that patterns a circuit pattern after coating, such as a lithography process, thereby enabling the construction of an efficient process, para. [0175-0181]).
Regarding claims 12 and 28, Choon teaches the recited limitations with respect to claims 10 and 24. Choon further teaches, wherein the structuring of the layer of the conductive material is performed by lithography; and/or wherein the structuring of the layer of the further conductive material is performed by lithography (a circuit pattern can be formed by printing conductive ink on the substrate during the first coating layer formation step or the second coating layer formation step. In addition, the method may further include a circuit pattern forming step of forming the circuit pattern by patterning the first coating layer or the second coating layer through photolithography, para. [0026-0027]).
Regarding claim 13, Choon teaches the recited limitations with respect to claim 1. Choon further teaches, the method according to claim 1, wherein the method is part of a sheet-to-sheet-process, a roll-to-sheet-process or a roll-to-roll-process (para. [0172]).
Claim(s) 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Choon as applied to claims 1 and 16 above, and further in view of Akiko (JP 2015005763, one of the prior arts listed in 12/20/2024 IDS).
Regarding claims 2 and 17, Choon does not teach, a bending radius. However, Akiko teaches, a method of forming a printed circuit board including forming through holes, structured deposition of first and second conductive layers and forming conductive traces, in which, the substrate comprises a flexible, insulating material so that the substrate comprises at least in some areas a target bending radius between 0,5 mm and 5 mm (a bending radius of 0.38 mm, para. [0104]). Therefore, in view of the teachings of Akiko, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of forming a double sided flexible circuit board of Choon and to replace the flexible substrate with the flexible wiring board 100 as Akiko taught in para. [0104] so that it enables improving the folding resistance of the wiring board.
Claim(s) 5-6, 11, 20-21 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Choon as applied to claims 1 and 16 above, and further in view of Dan (US 20210195762).
Regarding claims 5-6 and 20-21, Choon does not teach, a protective layer. However, Dan teaches, a method comprising forming through holes in an electrically insulating substrate in Figs. 1 and 2, structured deposition of conductive material so that the walls of the through holes are covered by the conductive material in which,
5. The method according claim 1, wherein the substrate comprises a first protective foil adhered to the second main surface region of the substrate and wherein the method additionally, comprises removing the first protective foil from the second main surface region of the substrate after the forming of the through-hole in the substrate (printed circuit board may further include a protective layer… protective layer is formed on the surfaces that is, the upper surface and the lower surface of the base substrate 110 of the printed circuit board…terminal part is formed on the printed circuit board after partially removing the protective layer, para. [0051-0052]).
6. The method according to claim 5, wherein the substrate comprises a second protective foil adhered to the first main surface region of the substrate and wherein the method additionally, comprises removing the second protective foil from the first main surface region of the substrate after the forming of the through-hole in the substrate (para. [0051-0052]).
20. The method according to claim 16, wherein the substrate comprises a first protective foil adhered to the second main surface region of the substrate and wherein the method additionally, comprises removing the first protective foil from the second main surface region of the substrate after the forming of the through-hole in the substrate (printed circuit board may further include a protective layer… protective layer is formed on the surfaces that is, the upper surface and the lower surface of the base substrate 110 of the printed circuit board…terminal part is formed on the printed circuit board after partially removing the protective layer, para. [0051-0052]).
21. The method according to claim 20, wherein the substrate further comprises a second protective foil adhered to the first main surface region of the substrate and wherein the method additionally, comprises removing the second protective foil from the first main surface region of the substrate after the forming of the through-hole in the substrate (para. [0051-0052]).
Therefore, in view of the teachings of Dan, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of forming a double sided flexible circuit board of Choon and forming a protective foils on the upper surface and the lower surface of the insulating substrate so that it enables protecting the organic substrate layer.
Regarding claims 11 and 27, Choon does not teach, depositing conducting material is performed by sputtering or evaporation. However, Dan further teaches,
11. The method according to claim 10, wherein the depositing of the conductive material on the first main surface region of the substrate to form the layer of the conductive material is performed by sputtering or evaporation; and/or wherein the depositing of the further conductive material on the second main surface region of the substrate to form the layer of the further conductive material is performed by sputtering or evaporation (thin seed layer 216 may be formed through a deposition process or a sputtering process, para. [0063]).
27. The method according to claim 26, wherein the depositing of the conductive material on the first main surface region of the substrate to form the layer of the conductive material is performed by sputtering or evaporation; and/or wherein the depositing of the further conductive material on the second main surface region of the substrate to form the layer of the further conductive material is performed by sputtering or evaporation (thin seed layer 216 may be formed through a deposition process or a sputtering process, para. [0063]).
Therefore, in view of the teachings of Dan, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of forming a double sided flexible circuit board of Choon and deposing the conducting materials by sputtering as Dan disclosed in para. [0063] on the upper surface and the lower surface of the insulating substrate so that it enables forming a wiring board having low permittivity and high speed processing to implement the high clock and the narrow line width as Dan disclosed in para. [0011].
Claim(s) 8 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Choon as applied to claims 1 and 16 above, and further in view of Karavakis (US 20200389980).
Regarding claims 8 and 23, Choon does not teach, an ultrasonic bath and/or using plasma surface cleaning. However, Karavakis teaches, a method of manufacturing a flexible circuit board, in which,
8. The method according to claim 7, wherein the cleaning of the substrate with the through-hole is performed using an ultrasonic bath and/or using plasma surface cleaning (cleaned or de-smeared using plasma cleaning, para. [0068]).
23. The method according to claim 22, wherein the cleaning of the substrate with the through-hole is performed using an ultrasonic bath and/or using plasma surface cleaning (cleaned or de-smeared using plasma cleaning, para. [0068]).
Therefore, in view of the teachings of Karavakis, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of forming a double sided flexible circuit board of Choon and to include a plasma cleaning process so that it enables removing the unwanted residues or by-products left behind by laser or mechanical drilling as Karavakis disclosed in para. [0068].
Conclusion
Prior art Tsai (US 20220272840) teaches, a method comprising providing an electrically insulating substrate; forming a through-hole in the substrate; structured deposition of conductive material on the first main surface region of the substrate; and structured deposition of further conductive material on the second main surface region of the substrate so that second conductive traces are formed on the second main surface region of the substrate.
Prior art Bai (US 20180324958) teaches, a method including providing an electrically insulating substrate; forming a through-hole in the substrate; structured deposition of conductive material on the first main surface region of the substrate, forming first conductive traces; and structured deposition of further conductive material on the second main surface region of the substrate so that second conductive traces are formed on the second main surface region of the substrate.
Prior art Chauhan (US 20150084207) teaches, a method including providing an electrically insulating substrate; forming a through-hole in the substrate; structured deposition of conductive material on the first main surface region of the substrate, forming first conductive traces; and structured deposition of further conductive material on the second main surface region of the substrate so that second conductive traces are formed on the second main surface region of the substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
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