DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Response to Remarks/Arguments
With respect to the rejection of claim 1 under 35 USC 102(a)(1), Applicant’s arguments filed 12/15/2025 have been fully considered but are moot in view of new ground rejections.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-12, and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimura ( US 6,845,184 B1).
Regarding claim 1, Yoshimura teaches a multi-chip system comprising:
a first chip (Fig. 1, 1a, col. 5, line 23, IC chips 1a-1d) including a first footprint area (footprint area of 1a);
a second chip (1d) including a second footprint area (footprint area of 1d);
a molding compound layer (Fig. 33, col. 35, lines 66-67, a chip layer 350) that encapsulates the first chip and the second chip (col. 35, lines 60-62, IC chips may be encapsulated; Fig. 33, col. 36, lines 1-2, two chips 351 and 352 are encapsulated in a dielectric film);
a routing layer (Fig. 33, 302) directly on and spanning across the molding compound layer (350), the first chip and the second chip (351, 352);
an interfacing bar (Fig. 33, col. 36, 336, 324a, 328) bonded to the routing layer (336, 324s and 328 bonded to 302 via 320), wherein the interfacing bar is electrically coupled with the first chip and the second chip (Fig. 33, 330, 332, contact pads 332, electrical traces 330), the interfacing bar including:
an electrical-to-optical converter component (Fig. 1, electrical to optical switch 26, col. 5, lines 64-67; Fig. 6, light emitting device 36a, 36b, col. 10, lines 38-40; col. 36, lines 23-33, VCSEL, PD, Fig. 33, 336; col. 36, lines 2-3, VSEL emitter device 336);
an optical-to-electrical converter component (Fig. 1, 28, Fig. 4-1, col. 8, lines 53-56, photo-detector device 28c; col. 36, lines 23-33, VCSEL, PD; Fig. 33, col. 36, line11, photo-detector device 328 ); and
one or more waveguides extending between the electrical-to-optical converter component and the optical-to-electrical converter component (col. 5, lines 40-41, waveguides 24, signals between the chips are conveyed optically by waveguide 24; col. 8, lines 53-56, waveguide 24f; Fig. 33, col. 36, lines 1-22, waveguide 324a);
wherein the interface bar that is bonded to the routing layer extends underneath only a first portion of the first footprint area (Fig. 1, overlapped area of 26a and 24d with 1a; col. 5, line 27, opto-electronic switching device 26a) and only a second portion of the second footprint area (Fig. 1, overlapped area of 28c and 24f with 1d; col 5, lines 27-28, photo-detector device 28c), wherein the first portion is smaller than the first footprint area and the second portion is smaller than the second footprint area (Fig. 1, the overlapped areas are smaller than the chip areas).
Regarding claim 2, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system further comprising a third chip (Fig. 1, 1b, 1c) coupled with the interfacing bar along a longitudinal length of the interfacing bar (24), wherein the second chip (1d) is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip (1b, 1c);
wherein the third chip includes a third footprint area (the footprint area of 1c) and the interfacing bar extends underneath a third portion of the third footprint area (the overlap between 1c and 24e) and the third portion is smaller than the third footprint area (the overlap area is smaller than the footprint area of 1c).
Regarding claim 3, all the limitations of claim 2 are taught by Yoshimura.
Yoshimura further teaches the system, wherein the interfacing bar comprises a semiconductor substrate (Fig. 4-1, 12, col. 5, line 25) and a routing layer over the semiconductor substrate (), the routing area including one or more metal wiring layers (Fig. 5-1, 30, 32, col. 9, lines 50-52).
Regarding claim 4, all the limitations of claim 3 are taught by Yoshimura.
Yoshimura further teaches the system, wherein the first chip and the third chip are electrically connected through the one or more metal wiring layers (Fig. 5-1, 30, 32, col. 9, lines 50-52).
Regarding claim 5, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is bonded to an outside of the routing layer (Fig. 33, 320, 302).
Regarding claim 6, all the limitations of claim 5 are taught by Yoshimura.
Yoshimura further teaches the system further comprising an underfill material encapsulating the plurality of solder bumps between the interfacing bar and the routing layer (col. 38, lines 1-2, underfill, solder joints).
Regarding claim 7, all the limitations of claim 6 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is laterally adjacent a plurality of ball grid array (BGA) solder bumps (col. 38, lines 1-2, underfill, solder joints).
Regarding claim 9, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is embedded in 2.5D package structure (col. 35, lines 59-65, active substrate layers to form 3-d multichip module).
Regarding claim 10, all the limitations of claim 9 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is laterally adjacent a plurality of conductive pillars in the 2.5D package structure (Fig. 33, col. 36, line 16, electrical vias 333).
Regarding claim 11, all the limitations of claim 10 are taught by Yoshimura.
Yoshimura further teaches the system wherein the routing layer includes a top redistribution layer (RDL), a bottom RDL, and an insulating material between the top RDL and the bottom RDL, wherein the interfacing bar is embedded in the insulating material (Fig. 34, 320 between two 350).
Regarding claim 12, all the limitations of claim 11 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is bonded to the top RDL of the routing layer with a plurality of solder bumps (Figs. 33-35, 332, col. 36, line 16, contact pads 332), and further comprising an underfill material encapsulating the plurality of solder bumps between the interfacing bar and the top RDL (col. 38, lines 1-2, underfill, solder joints).
Regarding claim 14, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is coupled with a first input output region along a first chip edge of the first chip, and is coupled with a second input/output region that is internal to chip edges of the second chip (Fig. 6, 36a, 28c).
Regarding claim 15, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system wherein the first chip is a first logic chip (col. 38, lines 61-62, processor/memory chips).
Regarding claim 16, all the limitations of claim 15 are taught by Yoshimura.
Yoshimura further teaches the system wherein the second chip is a memory chip (col. 38, lines 61-62, processor/memory chips).
Regarding claim 17, all the limitations of claim 15 are taught by Yoshimura.
Yoshimura further teaches the system wherein the second chip is a second logic chip (col. 38, lines 61-62, processor/memory chips).
Regarding claim 18, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system wherein the first chip and the second chip are both memory chips (col. 38, lines 61-62, processor/memory chips).
Regarding claim 19, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system further comprising: a third chip coupled with the interfacing bar along a longitudinal length of the interfacing bar (Fig. 136, left LSI), wherein the second chip is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip (Fig. 136, right LSI); and
a second interfacing bar coupled with the first chip and the third chip, the second interfacing bar including a die-to-die routing electrically connecting the first chip and the third chip within one or more metal routing layers of the second interfacing bar (Fig. 136, Fig. 131, connections via waveguide and electrical MCM).
Regarding claim 20, all the limitations of claim 1 are taught by Yoshimura.
Yoshimura further teaches the system wherein the interfacing bar is flexible (Figs. 136-137, col. 4, lines 58-60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura ( US 6,845,184 B1).
Regarding claim 8, all the limitations of claim 6 are taught by Yoshimura.
Yoshimura further teaches the system wherein the plurality of solder bumps is a plurality of micro bumps (col. 5, lines 33-34, solder bumps, micro bumps is well-known in the art as a type of solder bumps).
Regarding claim 13, all the limitations of claim 12 are taught by Yoshimura.
Yoshimura further teaches the system wherein the plurality of solder bumps is a plurality of micro bumps (col. 5, lines 33-34, solder bumps, micro bumps is well-known in the art as a type of solder bumps).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844
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