DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Remarks/Arguments
With respect to the rejection of claim 1 under 35 USC 102, Applicant's arguments filed 05/12/2026 have been fully considered but are moot in view of new grounds of rejection set forth herein as necessitated by Applicant's amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura ( US 6,845,184 B1) in view of Dutta (US 8,766,284 B1).
Regarding claim 1, Yoshimura teaches a multi-chip system comprising:
a first chip (Fig. 1, 1a, col. 5, line 23, IC chips 1a-1d) including a first footprint area (footprint area of 1a);
a second chip (1d) including a second footprint area (footprint area of 1d);
a molding compound layer (Fig. 33, col. 35, lines 66-67, a chip layer 350) that encapsulates the first chip and the second chip (col. 35, lines 60-62, IC chips may be encapsulated; Fig. 33, col. 36, lines 1-2, two chips 351 and 352 are encapsulated in a dielectric film);
a routing layer (Fig. 33, 302) directly on and spanning across the molding compound layer (350), the first chip and the second chip (351, 352);
an interfacing bar (Fig. 33, col. 36, 336, 324a, 328) bonded to the routing layer (336, 324s and 328 bonded to 302 via 320), wherein the interfacing bar is electrically coupled with the first chip and the second chip (Fig. 33, 330, 332, contact pads 332, electrical traces 330), the interfacing bar including:
an electrical-to-optical converter component (Fig. 1, electrical to optical switch 26, col. 5, lines 64-67; Fig. 6, light emitting device 36a, 36b, col. 10, lines 38-40; col. 36, lines 23-33, VCSEL, PD, Fig. 33, 336; col. 36, lines 2-3, VSEL emitter device 336);
an optical-to-electrical converter component (Fig. 1, 28, Fig. 4-1, col. 8, lines 53-56, photo-detector device 28c; col. 36, lines 23-33, VCSEL, PD; Fig. 33, col. 36, line11, photo-detector device 328 ); and
one or more waveguides extending between the electrical-to-optical converter component and the optical-to-electrical converter component (col. 5, lines 40-41, waveguides 24, signals between the chips are conveyed optically by waveguide 24; col. 8, lines 53-56, waveguide 24f; Fig. 33, col. 36, lines 1-22, waveguide 324a);
wherein the interface bar that is bonded to the routing layer extends underneath only a first portion of the first footprint area (Fig. 1, overlapped area of 26a and 24d with 1a; col. 5, line 27, opto-electronic switching device 26a) and only a second portion of the second footprint area (Fig. 1, overlapped area of 28c and 24f with 1d; col 5, lines 27-28, photo-detector device 28c), wherein the first portion is smaller than the first footprint area and the second portion is smaller than the second footprint area (Fig. 1, the overlapped areas are smaller than the chip areas).
Yoshimura does not explicitly teach the system wherein the interfacing bar is a discrete device including multiple discrete components.
Dutta teaches a system, wherein the interfacing bar (Fig. 4, 112, col. 9, line 20, optical waveguide 112) is a discrete device including multiple discrete components (Fig. 6, 162, 164, col. 10, lines 20-21, discrete optical components, for example, emitters 162 and photodetectors 164 are bonded).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the discrete interfacing bar of Dutta to the teachings of Yoshimura in order to utilize existing available chip package and PCB technology so that additional modification of chip package is not necessary and thus achieve optical interconnections in cost-effective manner suitable for practical electronics applications (Dutta, col. 4, lines 51~60).
Regarding claim 2, all the limitations of claim 1 are taught by Yoshimura in view of Dutta.
Yoshimura further teaches the system further comprising a third chip (Fig. 1, 1b, 1c) coupled with the interfacing bar along a longitudinal length of the interfacing bar (24), wherein the second chip (1d) is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip (1b, 1c);
wherein the third chip includes a third footprint area (the footprint area of 1c) and the interfacing bar extends underneath a third portion of the third footprint area (the overlap between 1c and 24e) and the third portion is smaller than the third footprint area (the overlap area is smaller than the footprint area of 1c).
Regarding claim 3, all the limitations of claim 2 are taught by in view of Dutta.
Yoshimura further teaches the system, wherein the interfacing bar comprises a semiconductor substrate (Fig. 4-1, 12, col. 5, line 25) and a routing layer over the semiconductor substrate (), the routing area including one or more metal wiring layers (Fig. 5-1, 30, 32, col. 9, lines 50-52).
Regarding claim 4, all the limitations of claim 3 are taught by in view of Dutta.
Yoshimura further teaches the system, wherein the first chip and the third chip are electrically connected through the one or more metal wiring layers (Fig. 5-1, 30, 32, col. 9, lines 50-52).
Regarding claim 5, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is bonded to an outside of the routing layer (Fig. 33, 320, 302).
Regarding claim 6, all the limitations of claim 5 are taught by in view of Dutta.
Yoshimura further teaches the system further comprising an underfill material encapsulating the plurality of solder bumps between the interfacing bar and the routing layer (col. 38, lines 1-2, underfill, solder joints).
Regarding claim 7, all the limitations of claim 6 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is laterally adjacent a plurality of ball grid array (BGA) solder bumps (col. 38, lines 1-2, underfill, solder joints).
Regarding claim 8, all the limitations of claim 6 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the plurality of solder bumps is a plurality of micro bumps (col. 5, lines 33-34, solder bumps, micro bumps is well-known in the art as a type of solder bumps).
Regarding claim 9, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is embedded in 2.5D package structure (col. 35, lines 59-65, active substrate layers to form 3-d multichip module).
Regarding claim 10, all the limitations of claim 9 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is laterally adjacent a plurality of conductive pillars in the 2.5D package structure (Fig. 33, col. 36, line 16, electrical vias 333).
Regarding claim 11, all the limitations of claim 10 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the routing layer includes a top redistribution layer (RDL), a bottom RDL, and an insulating material between the top RDL and the bottom RDL, wherein the interfacing bar is embedded in the insulating material (Fig. 34, 320 between two 350).
Regarding claim 12, all the limitations of claim 11 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is bonded to the top RDL of the routing layer with a plurality of solder bumps (Figs. 33-35, 332, col. 36, line 16, contact pads 332), and further comprising an underfill material encapsulating the plurality of solder bumps between the interfacing bar and the top RDL (col. 38, lines 1-2, underfill, solder joints).
Regarding claim 13, all the limitations of claim 12 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the plurality of solder bumps is a plurality of micro bumps (col. 5, lines 33-34, solder bumps, micro bumps is well-known in the art as a type of solder bumps).
Regarding claim 14, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is coupled with a first input output region along a first chip edge of the first chip, and is coupled with a second input/output region that is internal to chip edges of the second chip (Fig. 6, 36a, 28c).
Regarding claim 15, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the first chip is a first logic chip (col. 38, lines 61-62, processor/memory chips).
Regarding claim 16, all the limitations of claim 15 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the second chip is a memory chip (col. 38, lines 61-62, processor/memory chips).
Regarding claim 17, all the limitations of claim 15 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the second chip is a second logic chip (col. 38, lines 61-62, processor/memory chips).
Regarding claim 18, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the first chip and the second chip are both memory chips (col. 38, lines 61-62, processor/memory chips).
Regarding claim 19, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system further comprising: a third chip coupled with the interfacing bar along a longitudinal length of the interfacing bar (Fig. 136, left LSI), wherein the second chip is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip (Fig. 136, right LSI); and
a second interfacing bar coupled with the first chip and the third chip, the second interfacing bar including a die-to-die routing electrically connecting the first chip and the third chip within one or more metal routing layers of the second interfacing bar (Fig. 136, Fig. 131, connections via waveguide and electrical MCM).
Regarding claim 20, all the limitations of claim 1 are taught by in view of Dutta.
Yoshimura further teaches the system wherein the interfacing bar is flexible (Figs. 136-137, col. 4, lines 58-60).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEOKJIN KIM/Primary Examiner, Art Unit 2845
Prosecution Insights