DETAILED ACTION
Claims 1-22 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 10/23/2025 for application number 18/481,990.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 12 recite the limitation "the static memory" in the third paragraph of the claims. There is insufficient antecedent basis for this limitation in the claim.
Claims 1 and 12 recite a first component and a second component. More specifically, “the first component is one of the main processor, the coprocessor, and the controller” and “the second component is one of the controller and the main processor.” These descriptions have overlapping components. For example, the first and second component may both be the main processor. Examiner is unsure if this means the first and second component are meant to be the same or different. For the purposes of examination, the first and second component will be interpreted as the same (main processor).
Claims 2-11 and 13-22 are also rejected as incorporating the deficiencies of the rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hodgson et al. (US 2015/0095701 A1).
Regarding claim 1, Hodgson teaches a method for resetting a processor, suitable for a computer device (devices of Figures 1, 4 and 5) comprising a controller (Figure 4, MMU 441-443), a main processor (Figure 4, CPU 1 400 and “the first processor 400 may be considered to be a host processor.” Par 0046), a coprocessor (Figure 4, CPU 2 410 and CPU 3 420), and a random-access memory (Figure 1, volatile memory 120 and “the volatile memory 120 may be any suitable volatile memory, for example double data rate (DDR) synchronous random access memory (SRAM).” Par 0028), the method comprising:
obtaining a complete image file corresponding to the coprocessor by a first component of the computer device (“The non-volatile memory 110 may store instructions and data necessary for the processor to start executing, for example a file 111. ” Par 0029 and “The host processor may carry out some management functionality with respect to the system and the other processors. For example, the host processor may be configured to reset the other processors” par 0046 and Figures 1 and 6) [each file is associated with a respective processor, see paragraph 6], and loading the complete image file into a reference space in the random- access memory by the first component (“On boot-up, a copy (or image) 121 of the file 111 may be made and written to the volatile memory 120.” Par 0030 and “The duplicate … of the file…is stored in a second section of the first memory.” par 0009 and paragraphs 36-38 and Figures 1 and 6) [the duplicate data/second section corresponds to the reference space], wherein the random-access memory comprises a specific space corresponding to the coprocessor (“The file may comprise data information and the data information is stored in a first section of the first memory." par 0009 and “the first memory is a volatile memory of the multiprocessor system.” par 0005 and Figure 5) [the first section corresponds to the specific space;], and the first component is one of the main processor, the coprocessor, and the controller [the host (main) processor loads the information in memory, corresponding to the first component], wherein the reference space is a first designated random-access memory region configured to store said complete image file (“The duplicate…of the file…is stored in a second section of the first memory.” par 0009), and the specific space is a second designated random-access memory region, distinct from the reference space, configured to store the complete image file and from which the coprocessor executes (“The file may comprise data information and the data information is stored in a first section of the first memory… The data information stored in the first section of the first memory may be configured to be modified during the operation of the processor.” par 0009);
loading the complete image file stored in the reference space into the specific space corresponding to the coprocessor by a second component of the computer device (“Resetting the processor may comprise: overwriting the first section of the file with the data information stored in the second section; and resetting the processor using the file.” par 0011 and “When it is determined that the processor is to be reset, the copy 122 may be used to overwrite the corresponding section of the image file 121” par 0038 and “the host processor may control the updating of the duplicate data section.” par 0068), thereby enabling a reset of the coprocessor independently of an access status of the static memory of the computer device (“The processor may then be reset from the image file 121 stored in the volatile memory without having to reload the image file from the file 111 in the non-volatile memory.” par 0038), and validating the complete image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset (“The method may further comprise: determining that the first section of the first memory has been modified in error… Resetting the processor may comprise: overwriting the first section of the file with the data information stored in the second section;” Par 0011 and “the processor may be reset to a previous instruction at which the duplicate data section was last updated and known to be valid.” Par 0057 and “The duplicate…of the file may be maintained in a valid state” par 0013) [the validation occurs by restoring the corrupted data using a known valid backup (stored in second section) immediately before reset], wherein the second component is one of the controller and the main processor [the host (main) processor loads the file into the specific space and updates the duplicate file, corresponding to the second component]; and
resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid (“Resetting the processor may comprise: overwriting the first section of the file with the data information stored in the second section; and resetting the processor using the file.” par 0011) [overwriting the first section (specific space) with data from reference space ensures the image file is valid; this file from the first section (specific space) is then used to reset the processor].
Claim 12 corresponds to claim 1 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6, 13-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hodgson in view of Ghetie et al. (US 2020/0110880 A1).
Regarding claim 2, Hodgson teaches the method of claim 1, wherein the first component is the main processor or the coprocessor (Figure 1, processor 101), the second component is the controller (Figure 4, MMU 441, 442, 443), a security permission of the main processor is higher than a security permission of the coprocessor (“the host processor may be configured to reset the other processors and handle potential errors in the system.” par 0046) [the host processor having authority to reset and manage the other processors demonstrates higher level of security permission/control over the system].
However, Hodgson does not explicitly teach and before the step of validating the complete image file by the second component, the method further comprises: holding a plurality of reset signals corresponding to the main processor and the coprocessor by the controller in response to determining that the coprocessor needs to be reset and the main processor needs to be reset together; disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the controller in response to determining that the complete image file is not yet loaded into a static memory of the computer device; wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises: loading/updating the complete image file stored in the specific space into the static memory and releasing the reset signals corresponding to the main processor and the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal.
In the analogous art, Ghetie teaches before the step of validating the complete image file by the second component, the method further comprises:
holding a plurality of reset signals corresponding to the main processor and the coprocessor by the controller in response to determining that the coprocessor needs to be reset and the main processor needs to be reset together (“In pre-boot only one CPU is powered up and other external devices (e.g., BMC 119 and/or I/O hub 125) are kept at complete rest.” Par 0036 and “At 501, one of the CPUs of the platform is powered up by the security circuitry 105. Other platform components that access firmware are kept in reset (e.g., BMC 119 and I/O hub 125) are kept in reset at 503.” Par 0041 Figure 1 and 5) [the “kept in reset” directly shows holding of reset signals; security circuitry has control over the main processor (CPU); security circuitry manages reset of both CPUs in the same pre-boot operation, triggered by detection of a firmware attack, etc., which corresponds to resetting the main processor and coprocessor together; this step occurs before the calculation of firmware signatures, see Figure 5];
disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the controller in response to determining that the complete image file is not yet loaded into a static memory of the computer device (“If a recovery needs to be made, the security circuitry 105 is engaged to either move the gold image to the active partition (if proper to do so based on a security check), remote toggle a reset, or use a fail-safe radio frequency identification (RFID) device to receive a command.” Par 0040 and “If the active partition is corrupted, the golden image is used to restore the active partition 203 while wiping it clean.” par 0033 and Figure 5) [the gold image corresponds to the complete image file; the security circuitry loads the complete image from reference space to active partition (specific space), which would require disabling and enabling write-protection (which is an obvious and necessary step), in response to determining a recovery needs to be made/ image is not loaded or validated];
wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises:
loading/updating the complete image file stored in the specific space into the static memory and releasing the reset signals corresponding to the main processor and the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal (“performing secure pre-boot operations using at least a security circuit, powering down direct current (DC) power to any hardware processor in operation during secure pre-boot, and powering on DC power to hardware processors and performing a normal boot… the secure pre-boot operations comprise powering up one hardware processor in a plurality of hardware processors and holding components that access firmware in reset, holding other platform components that access firmware in reset…determining that the active partition is invalid, and restoring the active partition with the recovery partition;” Par 0072) [this shows the security circuitry (controller) loading the complete image file (recovery partition) into the specific space and then releasing reset signals (by powering on DC power) to the main processor and coprocessors (under BRI, enabled to participate in normal boot after reset) allowing them to perform the reset operation based on newly loaded image].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hodgson and Ghetie before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Ghetie to hold reset signals and disable the write/read access addresses the need for information sharing during an error. This circuitry that conducts signature verification and remote toggling of an error would enhance platform security and reliability, also preventing PDOS scenarios. (Ghetie, paragraph 43)
Claim 13 corresponds to claim 2 and is rejected accordingly.
Regarding claim 3, Hodgson and Ghetie teach the method of claim 2. Ghetie further teaches wherein the method further comprises, after the step of holding the reset signals corresponding to the main processor and the coprocessor by the second component:
disabling a write-protect function of the specific space, loading the complete image file from the static memory into the specific space, and enabling the write-protect function of the specific space by the controller in response to determining that the complete image file is loaded/updated into the static memory of the computer device (“If the active partition is corrupted, the golden image is used to restore the active partition 203 while wiping it clean.” Par 0033 and “After the pre-boot is complete (e.g., secure boot or recovery is complete), security circuitry removes the direct current (DC) power to the CPU at 405.” Par 0038 and “After DC power down, security circuitry restores the DC power and the CPU(s), I/O hub 125, and BMC 119 are enabled and booted as normal at 407.” Par 0039 Figure 1-4) [the active partition may correspond to the specific space; wiping it clean would include disabling write-protect before writing and enabling it afterwards to secure restored image; after pre-boot is complete, the controller releases the reset signals].
Claim 14 corresponds to claim 3 and is rejected accordingly.
Regarding claim 4, Hodgson teaches the method of claim 1, wherein the first component is the main processor or the coprocessor (Figure 1, processor 101), the second component is the controller (Figure 4, MMUs 441-443), a security permission of the main processor is higher than a security permission of the coprocessor (“the host processor may be configured to reset the other processors and handle potential errors in the system.” par 0046) [the host processor having authority to reset and manage the other processors demonstrates higher level of security permission/control over the system].
However, Hodgson does not explicitly teach before the step of validating the complete image file stored in the specific space by the second component, the method further comprises: holding a reset signal corresponding to the coprocessor by the controller in response to determining that the coprocessor needs to be reset but the main processor does not need to be reset together; disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the controller; wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises: releasing the reset signal corresponding to the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal.
In the analogous art, Ghetie teaches before the step of validating the complete image file stored in the specific space by the second component, the method further comprises:
holding a reset signal corresponding to the coprocessor by the controller in response to determining that the coprocessor needs to be reset but the main processor does not need to be reset together (“At 501, one of the CPUs of the platform is powered up by the security circuitry 105. Other platform components that access firmware are kept in reset (e.g., BMC 119 and I/O hub 125) are kept in reset at 503. As stated previously, this is typically done via the security circuitry 105 with the core CPLD 107.” Par 0041, Ghetie) [in this case, one main processor is powered up, not reset together with other elements, including coprocessor; this occurs before firmware validation during pre-boot];
disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the controller (“If the active partition is corrupted, the golden image is used to restore the active partition 203 while wiping it clean” par 0033, Ghetie) [wiping it clean implicitly includes disabling write-protect before writing and enabling it afterwards to secure restored image];
wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises:
releasing the reset signal corresponding to the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal (“After DC power down, security circuitry restores the DC power and the CPU(s), I/O hub 125, and BMC 119 are enabled and booted as normal at 407.” Par 0039, Ghetie) [the controller (security circuitry) releases rest signal (by restoring DC power) to the coprocessors; this allows them to conduct reset operation (boot as normal) based on complete image file, following its validation during pre-boot].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hodgson and Ghetie before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Ghetie to hold reset signals and disable the write/read access addresses the need for information sharing during an error. This circuitry that conducts signature verification and remote toggling of an error would enhance platform security and reliability, also preventing PDOS scenarios. (Ghetie, paragraph 43)
Claim 15 corresponds to claim 4 and is rejected accordingly.
Regarding claim 6, Hodgson teaches the method of claim 1. However, Hodgson does not explicitly teach further comprising: determining the coprocessor needs to be reset in response to determining that the computer device is booted or a reset operation of the coprocessor is triggered.
In the analogous art, Ghetie teaches determining the coprocessor needs to be reset in response to determining that the computer device is booted or a reset operation of the coprocessor is triggered (“a firmware attack, firmware update request, or a recovery image update request is detected at 409. For example, the active partition of the I/O hub flash 123 becomes corrupted. This causes a panic condition to be raised and a reboot into the pre-boot stage. If a recovery needs to be made, the security circuitry 105 is engaged,” par 0040) [the determination for recovery is in response to detecting a firmware attack, which may correspond to a trigger for a reset operation of the coprocessor].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hodgson and Ghetie before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Ghetie to enhance platform security and reliability, and prevent PDOS scenarios. (Ghetie, paragraph 43)
Claim 17 corresponds to claim 6 and is rejected accordingly.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hodgson in view of Lim (US 2004/0255111 A1).
Regarding claim 5, Hodgson teaches the method of claim 1, wherein the first component is the coprocessor (Figure 1, processor 101), the second component is the main processor (Figure 4, CPU 1 400), a security permission of the main processor is higher than a security permission of the coprocessor (“the host processor may be configured to reset the other processors and handle potential errors in the system.” par 0046) [the host processor having authority to reset and manage the other processors demonstrates higher level of security permission/control over the system].
However, Hodgson does not explicitly teach before the step of validating the complete image file stored in the specific space by the second component, the method further comprises: holding a reset signal corresponding to the coprocessor by the main processor in response to determining that the coprocessor needs to be reset; disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the main processor; wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises: loading the complete image file stored in the specific space into a static memory of the computer device and releasing the reset signal corresponding to the coprocessor by the main processor, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal.
In the analogous art, Lim teaches before the step of validating the complete image file stored in the specific space by the second component, the method further comprises:
holding a reset signal corresponding to the coprocessor by the main processor in response to determining that the coprocessor needs to be reset (“the main processor 100 can reset the coprocessor using a variety of methods, including for example, a method for recording a specific value in a specific register contained in the coprocessor 200, and a method for applying a signal to a reset terminal exposed to the outside of the coprocessor 200.” Par 0089) [main processor, which may act as a controller, can reset the coprocessor specifically, meaning the main processor can be reset or remain operational while coprocessor is reset; this reset may occur before file validation];
disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the main processor (“The main processor 100 reads code files of the boot module, the loader module, and the tiny flash file system from either the first flash memory 110 or the second flash memory 120, and moves the read code files to the internal RAM 205 of the coprocessor 200 for storage in the RAM 205.” Par 0082) [the main processor actively transfers and stores program files into coprocessor’s memory, meaning control over write functions, which under BRI, includes managing any write-protect features];
wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises:
loading the complete image file stored in the specific space into a static memory of the computer device (Figure 10, step 523; the program code is loaded into the memory) and releasing the reset signal corresponding to the coprocessor by the main processor, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal (“After completing the transmission of the boot, loader, and tiny flash file system code files of the coprocessor 200 to either the first flash memory 110 or the second flash memory 120, the main processor 100 then resets the coprocessor 200... method for applying a signal to a reset terminal exposed to the outside of the coprocessor 200.” Par 0083 and “Therefore, the coprocessor 200 is reset, and its PC (Program Counter) jumps to the entrance points of the boot, loader, and tiny flash file system code areas,” par 0084 and Figure 10) [the main processor acts as a controller in this case, and after resetting, subsequent operation may mean releasing of reset signals corresponding to the processor, see 517 in Figure 10].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hodgson and Lim before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Lim to add the functionality of firmware auto-recovery and coordinated loading and resetting operations of the device’s processors. Subsequent loading and resetting of processors as taught in Lim would be an obvious step to update the file to a “good version” and ensure system functionality after a booting sequence.
Claim 16 corresponds to claim 5 and is rejected accordingly.
Claims 7, 8, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hodgson and Ghetie in view of Lim.
Regarding claim 7, Hodgson and Ghetie teach the method of claim 6, wherein both the first component and the second component are the controller (Figure 4, MMUs 441-443). However, Hodgson and Ghetie do not explicitly teach a security permission of the main processor is lower than a security permission of the coprocessor, and before the step of validating the complete image file stored in the specific space by the second component, the method further comprises: holding a reset signal corresponding to the coprocessor by the controller in response to determining that the computer device is booted; loading the complete image file from a static memory of the computer device into the reference space and the specific space by the controller; wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises: enabling a write-protect function of the specific space and releasing the reset signal corresponding to the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal.
In the analogous art, Lim teaches a security permission of the main processor is lower than a security permission of the coprocessor (“Upon receiving a control signal from the main processor 100, the coprocessor 200 assumes direction of a specific function, and processes the specific function.” Par 0009 and “The coprocessor is comprised of a processor for operating application programs or specific functions requiring a high speed, for example, a GUI (Graphic User Interface), a multimedia codec, and similar devices.” Par 0039) [regarding the specific function, the coprocessor has higher authority compared to the main processor and this may include read functions, see paragraph 64] and before the step of validating the complete image file stored in the specific space by the second component, the method further comprises:
holding a reset signal corresponding to the coprocessor by the controller in response to determining that the computer device is booted (“main processor 100 can reset the coprocessor using a variety of methods, including for example, a method for recording a specific value in a specific register contained in the coprocessor 200, and a method for applying a signal to a reset terminal exposed to the outside of the coprocessor 200.” Par 0083) [under BRI, the reset terminal may correspond to when the computer device is booted];
loading the complete image file from a static memory of the computer device into the reference space and the specific space by the controller (“The main processor 100 reads code files of the boot module, the loader module, and the tiny flash file system from either the first flash memory 110 or the second flash memory 120, and moves the read code files to the internal RAM 205 of the coprocessor 200 for storage in the RAM 205.” Par 0082) [the main processor acts as a controller in this case; the internal RAM 205 may correspond to a specific space; the first or second memory may correspond to the reference space];
wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises:
enabling a write-protect function of the specific space and releasing the reset signal corresponding to the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal (“After finishing the transmission of the boot, loader, and tiny flash file system code files of the coprocessor 200 …main processor 100 resets the coprocessor 200. … Upon receiving the reset signal at step 617, the coprocessor 200 is reset. In this case, the external RAM 230 of the coprocessor 200 stores the boot, loader, and tiny flash file system code files of the coprocessor 200. Therefore, the coprocessor 200 is reset, and its PC (Program Counter) jumps to the entrance points of the boot, loader, and tiny flash file system code areas at step 619. The coprocessor 200 can then perform its booting function at step 621,” par 0089-0090) [the booting function from the loaded memory suggests that the coprocessor is now operational, under BRI, indicating that the write access is now enabled].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hodgson and Lim before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Lim to add the functionality of firmware auto-recovery and coordinated loading and resetting operations of the device’s processors. Subsequent loading and resetting of processors as taught in Lim would be an obvious step to update the file to a “good version” and ensure system functionality after a booting sequence.
Claim 18 corresponds to claim 7 and is rejected accordingly.
Regarding claim 8, Hodgson and Ghetie teach the method of claim 6, wherein both the first component and the second component are the controller (Figure 4, MMUs 441-443). Ghetie further teaches determining whether the specific space is reorganized (“A determination of if the active partitions 203 are valid is made at 511” par 0044 and Figure 5); maintaining the write-protect function of the specific space by the controller in response to that the specific space is not reorganized (“The SPI bus at the input of the flash devices is routed to the security circuitry 105 allowing for monitoring filtering of SPI flash transactions during normal boot… When a malicious transaction is detected, the corresponding chip-select is de-asserted by the security circuitry 105 to prevent the transaction for proceeding.” par 0030) [the controller monitors and filters transactions during normal boot; the de-assertion precents unauthorized writes, thereby maintaining a write-protect function]; disabling a write-protect function of the specific space, loading the complete image file from the reference space into the specific space, and enabling the write-protect function of the specific space by the controller in response to that the specific space is reorganized (“If the active partition is corrupted, the golden image is used to restore the active partition 203 while wiping it clean.” Par 0033 and “The security circuitry 105 gains access to the flash during a pre-boot mode,” par 0030 and “If a recovery needs to be made, the security circuitry 105 is engaged to either move the gold image to the active partition (if proper to do so based on a security check),” par 0040) [wiping it clean implicitly includes disabling write-protect before writing and enabling it afterwards to secure restored image; the controller accesses the flash (specific space) during reorganization (pre-boot mode) and moving (loading/writing) the image; this process also, under BRI, requires disabling and enabling write-protect functions on the specific space].
However, Hodgson and Ghetie do not explicitly teach a security permission of the main processor is lower than a security permission of the coprocessor, and before the step of validating the complete image file stored in the specific space by the second component, the method further comprises: holding a reset signal corresponding to the coprocessor by the controller in response to determining that the computer device is booted; wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises: releasing the reset signal corresponding to the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal.
In the analogous art, Lim teaches a security permission of the main processor is lower than a security permission of the coprocessor (“Upon receiving a control signal from the main processor 100, the coprocessor 200 assumes direction of a specific function, and processes the specific function.” Par 0009 and “The coprocessor is comprised of a processor for operating application programs or specific functions requiring a high speed, for example, a GUI (Graphic User Interface), a multimedia codec, and similar devices.” Par 0039) [regarding the specific function, the coprocessor has higher authority compared to the main processor and this may include read functions, see paragraph 64], and before the step of validating the complete image file stored in the specific space by the second component, the method further comprises:
holding a reset signal corresponding to the coprocessor by the controller in response to determining that the computer device is booted (“main processor 100 can reset the coprocessor using a variety of methods, including for example, a method for recording a specific value in a specific register contained in the coprocessor 200, and a method for applying a signal to a reset terminal exposed to the outside of the coprocessor 200.” Par 0083) [under BRI, the reset terminal may correspond to when the computer device is booted];
wherein the step of resetting the coprocessor based on the complete image file stored in the specific space by the second component in response to the second component determining that the complete image file stored in the specific space is valid comprises:
releasing the reset signal corresponding to the coprocessor by the controller, wherein the coprocessor performs a reset operation based on the complete image file stored in the specific space in response to the corresponding reset signal(“After finishing the transmission of the boot, loader, and tiny flash file system code files of the coprocessor 200 …main processor 100 resets the coprocessor 200. … Upon receiving the reset signal at step 617, the coprocessor 200 is reset. In this case, the external RAM 230 of the coprocessor 200 stores the boot, loader, and tiny flash file system code files of the coprocessor 200. Therefore, the coprocessor 200 is reset, and its PC (Program Counter) jumps to the entrance points of the boot, loader, and tiny flash file system code areas at step 619. The coprocessor 200 can then perform its booting function at step 621,” par 0089-0090) [the booting function from the loaded memory suggests that the coprocessor is now operational, under BRI, indicating that the write access is now enabled].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hodgson, Ghetie and Lim before him before the effective filing date of the claimed invention, to have modified Hodgson and Ghetie to incorporate the teachings of Lim to have a security permission of a coprocessor to be higher than that of a main processor for specific functions to add protection from potential vulnerabilities and attacks from external bad actors. In cases of a compromised main processor, higher security permissions for a coprocessor may maintain its contents.
Claim 19 corresponds to claim 8 and is rejected accordingly.
Claims 9-11, 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hodgson in view of Tan et al. (US 2007/0294745 A1).
Regarding claim 9, Hodgson teaches the method of claim 1, wherein the first component is the main processor or the coprocessor (Figure 1, processor 101), the second component is the controller (Figure 4, MMU 441, 442, 443). However, Hodgson does not explicitly teach a security permission of the main processor is lower than a security permission of the coprocessor.
In the analogous art, Tan teaches a security permission of the main processor is lower than a security permission of the coprocessor (The owner of the security processor 102 may have the highest level of control of the security system 100.” Par 0030 and Figure 1) [the security processor may correspond to a coprocessor’ this quote implies the coprocessor has higher security permission than the main processor (corresponding to the host CPU 104, Figure 1)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hodgson and Tan before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Tan because both Tan and Hodgson teach a circuit that has control over other system elements including the main processor. This circuit having a higher security permission will allow for automatic detection and recovery from firmware attacks.
The remainder of claim 9 is repeated in claim 2 above and is rejected accordingly.
Claim 20 repeats the same limitations as recited in claim 9 and is rejected accordingly.
Claims 10 and 21 correspond to claim 3 and are rejected accordingly.
Regarding claim 11, Hodgson teaches the method of claim 1, wherein the first component is the main processor or the coprocessor (Figure 1, processor 101), the second component is the controller (Figure 4, MMU 441, 442, 443).
However, Hodgson does not explicitly teach a security permission of the main processor is lower than a security permission of the coprocessor.
In the analogous art, Tan teaches a security permission of the main processor is lower than a security permission of the coprocessor (The owner of the security processor 102 may have the highest level of control of the security system 100.” Par 0030 and Figure 1) [the security processor may correspond to a coprocessor’ this quote implies the coprocessor has higher security permission than the main processor (corresponding to the host CPU 104, Figure 1)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hodgson and Tan before him before the effective filing date of the claimed invention, to have modified Hodgson to incorporate the teachings of Tan because both Tan and Hodgson teach a circuit that has control over other system elements including the main processor. This circuit having a higher security permission will allow for automatic detection and recovery from firmware attacks.
The remainder of claim 11 repeats the same limitation as recited in claim 4 and is rejected accordingly.
Claim 22 corresponds to claim 11 and is rejected accordingly.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176