Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action responds to the Application filed on 10/6/2023 and IDS filed on 11/20/2024, 1/03/2025, 6/19/2025, and 3/16/2026.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1-5, 11, and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Herberholz et al. (U.S. Pub. No. 2024/0111350 A1).
As per claim 1, Herberholz discloses:
An apparatus comprising:
a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit and sensors of the first sensor array configured to generate one or more first level indications of a condition of the integrated circuit (See Figure 2A, i.e. functional path 214 & monitor 298, See Figure 2B, i.e. timing monitor 136, See Para [0023]-[0024], i.e. XOR logic gate or similar comparison device…setup warning comparison logic (L1) may output the setup warning signal 254 when the desired timing margin is not met, See Para [0043], i.e. select functional paths and couple their observation points to nearby timing monitors, See Para [0053], i.e. for TMU_A, method 800 may scan functional paths [prior art monitor functional path using TMU_A is considered as the first sensor array]) ;
a second sensor array formed in the integrated circuit, sensors of the second sensor array having paths through the integrated circuit and sensors of the second sensor array configured to generate one or more second level indications of the condition of the integrated circuit (See Figure 2B, i.e. timing monitor Unit 136, See Para [0025], i.e. cluster 226 of path timing monitors or TMUs 208 … communicates via a digital control bus to a sensor group interface … sensor group interface has a digital bus connection to a control processor subsystem 148, See Para [0043], i.e. co-locate canary paths nearby the functional paths within the core circuitry and couple the canary paths to the timing monitors, See Para [0053], i.e. a number of warnings generated for canary paths monitored by TMU_B – [prior art monitor canary path using TMU_B is considered as the second sensor array); and
a monitor controller coupled to the first sensor array and to the second sensor array and configured to receive the one or more first level indications and to actuate the second sensor array in response to the one or more first level indications (See Figure 2B, i.e. timing monitor Unit 136, See Para [0025], i.e. cluster 226 of path timing monitors or TMUs 208 … communicates via a digital control bus to a sensor group interface … sensor group interface has a digital bus connection to a control processor subsystem 148, See Para [0053]-[0055], i.e. check a number of warnings generated in a specified period for each functional path monitored by TMU_A that exceeds a number of warnings generated for canary paths monitored by TMU_B – [prior art after determining warning for TMU_A, determine warning generated TMU_B in order to determine if re-calibration of the sensor is considered as the actuation of the actuate the second sensor array in response to the one or more first level indications, as cited above]).
As per claim 2, Herberholz discloses all of the features of claim 1 as discloses above wherein Herberholz also discloses wherein the indications comprise indications of setup timing margin conditions (See Para [0055]-[0056], i.e. minimum setup timing margins, See Para [0059]-[0060], i.e. checking a number of setup warnings).
As per claim 3, Herberholz discloses all of the features of claim 1 as discloses above wherein Herberholz also discloses wherein the integrated circuit has a plurality of logic paths, wherein the sensors of the first sensor array are configured to replicate operation of a respective logic path (See Figure 2A, i.e. functional path 214 & monitor 298, See Figure 2B, i.e. timing monitor 136, See Para [0023]-[0024], i.e. XOR logic gate or similar comparison device…setup warning comparison logic (L1) may output the setup warning signal 254 when the desired timing margin is not met, See Para [0043], i.e. select functional paths and couple their observation points to nearby timing monitors, See Para [0053], i.e. for TMU_A, method 800 may scan functional paths).
As per claim 4, Herberholz discloses all of the features of claim 1 as discloses above wherein Herberholz also discloses wherein the sensors of the second sensor array are configured to replicate a worst-case operation instance of the respective logic path (See Para [0031], i.e. a calibration of delays between the worst functional path and the canary path, See Para [0038]).
As per claim 5, Herberholz discloses all of the features of claim 1 as discloses above wherein Herberholz also discloses wherein the monitor controller comprises a toggle rate controller coupled to the first sensor array, the toggle rate controller configured to control a toggle rate of sensors of the second sensor array (See Para [0050], i.e. nominal frequency…increase clock frequency).
As per claim 11, Herberholz discloses all of the features of claim 1 as discloses above wherein Herberholz also discloses wherein the second sensor array comprises an aggregator configured to aggregate the one or more second level indications of the sensors of the second sensor array and to generate a margin code, and wherein the monitor controller receives the margin code (See Figure 2B, i.e. timing monitor Unit 136, See Para [0025], i.e. cluster 226 of path timing monitors or TMUs 208 … communicates via a digital control bus to a sensor group interface … sensor group interface has a digital bus connection to a control processor subsystem 148, See Para [0053]-[0055], i.e. check a number of warnings generated in a specified period for each functional path monitored by TMU_A that exceeds a number of warnings generated for canary paths monitored by TMU_B).
As per claim 12, Herberholz discloses all of the features of claim 1 as discloses above wherein Herberholz also discloses wherein the first sensor array comprises an aggregator configured to aggregate the one or more second level indications of the sensors of the first sensor array and to generate a margin code, and wherein the monitor controller receives the margin code to actuate the second sensor array in response to the margin code (See Figure 2B, i.e. timing monitor Unit 136, See Para [0025], i.e. cluster 226 of path timing monitors or TMUs 208 … communicates via a digital control bus to a sensor group interface … sensor group interface has a digital bus connection to a control processor subsystem 148, See Para [0053]-[0055], i.e. check a number of warnings generated in a specified period for each functional path monitored by TMU_A that exceeds a number of warnings generated for canary paths monitored by TMU_B).
Allowable Subject Matter
5. Claims 18-20 are allowed.
6. Claims 6-10 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 18: The closest prior art of record Herberholz et al. (U.S. Pub. No. 2024/0111350 A1) teach: A method comprising: generating one or more first level indications of a condition of an integrated circuit in a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit (See Figure 2A, i.e. functional path 214 & monitor 298, See Figure 2B, i.e. timing monitor 136, See Para [0023]-[0024], i.e. XOR logic gate or similar comparison device…setup warning comparison logic (L1) may output the setup warning signal 254 when the desired timing margin is not met, See Para [0043], i.e. select functional paths and couple their observation points to nearby timing monitors, See Para [0053], i.e. for TMU_A, method 800 may scan functional paths [prior art monitor functional path using TMU_A is considered as the first sensor array]).
The prior art does not teach: actuating a second sensor array in response to
the one or more first level indications falling below a threshold, sensors of the second sensor array having paths through the integrated circuit, and being more numerous than sensors of the first sensor array; and generating one or more second level indications of a condition of the integrated circuit in the second sensor array, as recited in independent claim 18.
With respect to claim 19: The closest prior art of record Herberholz et al. (U.S. Pub. No. 2024/0111350 A1) teach: A method comprising: generating one or more first level indications of a condition of an integrated circuit in a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit (See Figure 2A, i.e. functional path 214 & monitor 298, See Figure 2B, i.e. timing monitor 136, See Para [0023]-[0024], i.e. XOR logic gate or similar comparison device…setup warning comparison logic (L1) may output the setup warning signal 254 when the desired timing margin is not met, See Para [0043], i.e. select functional paths and couple their observation points to nearby timing monitors, See Para [0053], i.e. for TMU_A, method 800 may scan functional paths [prior art monitor functional path using TMU_A is considered as the first sensor array]).
The prior art does not teach the limitations: actuating a second sensor array in response to the one or more first level indications falling below a threshold, sensors of the second sensor array having paths through the integrated circuit; and
generating one or more second level indications of the condition of the integrated circuit in the second sensor array upon actuation, as recited in independent claim 19.
With respect to claim 20: The closest prior art of record Herberholz et al. (U.S. Pub. No. 2024/0111350 A1) teach: A computer-readable medium having instructions that when executed by the machine cause the machine to perform operations including: generating one or more first level indications of a condition of an integrated circuit in a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit (See Figure 2A, i.e. functional path 214 & monitor 298, See Figure 2B, i.e. timing monitor 136, See Para [0023]-[0024], i.e. XOR logic gate or similar comparison device…setup warning comparison logic (L1) may output the setup warning signal 254 when the desired timing margin is not met, See Para [0043], i.e. select functional paths and couple their observation points to nearby timing monitors, See Para [0053], i.e. for TMU_A, method 800 may scan functional paths [prior art monitor functional path using TMU_A is considered as the first sensor array]).
The prior art does not teach the limitations: actuating a second sensor array in response to the one or more first level indications falling below a threshold, sensors of the second sensor array having paths through the integrated circuit; and
generating one or more second level indications of the condition of the integrated circuit in the second sensor array upon actuation, as recited in independent claim 20.
With respect to claims 6-10 and 13-17: The prior art does not teach the limitations of claims 6, 10, 13, 14, 15, and 17 – wherein claims 7-9 depend on claim 6, wherein claim 16 depend on claim 15.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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