DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
Claims 1, 17 and 19 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 14 and 19 of U.S. Patent No. 12455996. Although the claims at issue are not identical, they are not patentably distinct from each other because following observation is made:
Instant Application
Patent No. US 12,455.996
1. An apparatus comprising: an integrated circuit having a logic path formed in the integrated circuit; a monitor circuit formed in the integrated circuit, the monitor circuit being configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time; and a monitor controller configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in a log with a corresponding time stamp and to determine a condition of the integrated circuit based on the diagnostic codes.
1. An apparatus comprising: an integrated circuit having a logic path formed in the integrated circuit; a monitor circuit formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time; a log to store the diagnostic code sequence; and a monitor controller configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in the log with a corresponding time stamp, to determine a condition of the integrated circuit based on the diagnostic code sequence that is stored in the log, and to initiate a remedial action in response to the condition of the integrated circuit.
17. A method comprising: monitoring a condition of a logic path formed in an integrated circuit at a monitor circuit formed in the integrated circuit near the logic path; generating a diagnostic code sequence to indicate the condition of the logic path over time; and determining a condition of the integrated circuit based on the diagnostic code sequence.
14. A method comprising: monitoring a condition of a logic path formed in an integrated circuit at a monitor circuit formed in the integrated circuit near the logic path; generating a diagnostic code sequence to indicate the condition of the logic path over time; storing the diagnostic code sequence in a log with a corresponding time stamp; and determining a condition of the integrated circuit based on the diagnostic code sequence that is stored in the log; and initiating a remedial action in response to the condition of the integrated circuit.
19. A computer-readable medium having instructions that when executed by the machine cause the machine to perform operations including: monitoring a condition of a logic path formed in an integrated circuit at a monitor circuit formed in the integrated circuit near the logic path; generating a diagnostic code sequence to indicate the condition of the logic path over time; and determining a condition of the integrated circuit based on the diagnostic code sequence.
19. A non-transitory computer-readable medium having instructions that when executed by the machine cause the machine to perform operations including: monitoring a condition of a logic path formed in an integrated circuit at a monitor circuit formed in the integrated circuit near the logic path; generating a diagnostic code sequence to indicate the condition of the logic path over time; storing the diagnostic code sequence in a log with a corresponding time stamp; determining a condition of the integrated circuit based on the diagnostic code sequence that is stored in the log; and initiating a remedial action in response to the condition of the integrated circuit.
As demonstrated, the claims 1, 14 and 19 of US Patent NO. 12,455.996 disclose all the features of claims 1, 17 and 19 of the instant application with minor obvious variations. Thus, it would have been obvious to one of ordinary skill in the art having the claims 1, 14 and 19 of Patent 12,455.996 to modify the claims to achieve the features of claims 1, 17 and 19 of the instant application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
As per claims 19-20, they are rejected because the applicant has provided evidence that the applicant intends the term "computer-readable medium” to include non-statutory matter. The applicant describes a computer-readable storage medium as including open ended language and thus it is reasonable to interpret it to include all possible mediums, including non-statutory mediums (see paragraph 0097). The words "storage" and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim(s) is/are drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter.
The Examiner suggests amending the claim(s) to read as a “non-transitory computer-readable storage medium”.
Allowable Subject Matter
Claims 4,7,9,11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Singh (Pub No. US 2019/0286179)
Regarding Claim 17 Sing discloses: a method [Fig.1] comprising: monitoring [circuit performance monitor 120 of Fig.1.] a condition [performance data collector 122, [0038]: "...the circuit performance monitor 120 may include a performance data collector 122. The performance data collector 122 may be configured to collect measured performance data of the one or more replica feedback paths, compare the measured performance data to a set of reference performance data, and generate performance differences between the measured performance data and the set of reference performance data based on the comparison.] of a logic path [[0036], Feedback path 106 of Fig.1] formed in an integrated circuit [Fig.1, item 100, Integrated Circuit, ] at a monitor circuit formed in the integrated circuit near the logic path; [[0037] The integrated circuit may further include a circuit performance monitor 120, which in turn may include one or more replica feedback paths of one or more replica circuit blocks (such as 112 and 114) corresponding to the one or more feedback paths in the one or more circuit blocks. For example, replica feedback path 116 may be configured to match the performance of feedback path 106, and replica feedback path 118 may be configured to match the performance of feedback path 108. The circuit performance monitor 120 is configured to monitor feedback path information of the one or more replica feedback paths. In some implementations, the replica feedback paths may be placed close to their corresponding feedback paths, for example the replica feedback path 116 may be placed in close proximity with the feedback path 106] generating a diagnostic code sequence to indicate the condition of the logic path over time; [performance data collector 122, [0038]: "...the circuit performance monitor 120 may include a performance data collector 122. The performance data collector 122 may be configured to collect measured performance data of the one or more replica feedback paths, compare the measured performance data to a set of reference performance data, and generate performance differences between the measured performance data and the set of reference performance data based on the comparison.] and determining a condition of the integrated circuit based on the diagnostic code sequence. [[0040]- [0041] "...the integrated circuit 200 may further include a circuit performance controller 202, which may include one or more performance adjusters 204. According to aspects of the present disclosure, the one or more performance adjusters 204 may be configured to determine one or more adjustment voltage values based at least in part on the feedback path information of the one or more replica feedback paths received from the circuit performance monitor 120, and adjust corresponding supply voltages of the one or more circuit blocks, for example circuit blocks 102 and 104, using the one or more adjustment voltage values measured during operation of the integrated circuit 200."…… "adjust corresponding supply voltages of the one or more circuit blocks..."In some implementations, the one or more performance adjusters 204 may be configured to determine one or more operating frequency values based at least in part on the feedback path information of the one or more replica feedback paths, where the feedback path information includes at least one of performance data or signal quality data of the one or more replica feedback paths, and adjust corresponding operating frequencies of the one or more circuit blocks using the one or more operating frequency values during operation of the integrated circuit....]
Regrading Claim 18, Singh discloses generating a health signal [adjustment voltage values] in response to the diagnostic codes; comparing the health signal to a health threshold; [[0044] the circuit parameters of the one or more circuit blocks includes at least one of: threshold voltages of the one or more circuit blocks, power usage of the one or more circuit blocks, electrical impedance of the one or more circuit blocks, operating frequencies of the one or more circuit blocks, or a combination thereof] and sending the health signal to a higher layer in response to the health signal crossing the health threshold. [[0040]- [0041] "...the integrated circuit 200 may further include a circuit performance controller 202, which may include one or more performance adjusters 204. According to aspects of the present disclosure, the one or more performance adjusters 204 may be configured to determine one or more adjustment voltage values based at least in part on the feedback path information of the one or more replica feedback paths received from the circuit performance monitor 120, and adjust corresponding supply voltages of the one or more circuit blocks, for example circuit blocks 102 and 104, using the one or more adjustment voltage values measured during operation of the integrated circuit 200]
Claim 19 is having similar limitations to that of the apparatus of claim 17.Accordingly, claim 19 is rejected under a similar rational as that of claim 17 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2,5-6,8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Singh (Pub No. US 2019/0286179) in view of O’Brien (Brien hereinafter) (Patent NO. US 5,550,841)
Regrading Claim 1, Singh teaches an apparatus [Fig.1] comprising: an integrated circuit [Fig.1, item 100, Integrated Circuit] having a logic path formed in the integrated circuit; [[0036], Feedback path 106 of Fig.1] a monitor circuit [circuit performance monitor 120 of Fig.1.] formed in the integrated circuit,[[0037] The integrated circuit may further include a circuit performance monitor 120, which in turn may include one or more replica feedback paths of one or more replica circuit blocks (such as 112 and 114) corresponding to the one or more feedback paths in the one or more circuit blocks. For example, replica feedback path 116 may be configured to match the performance of feedback path 106, and replica feedback path 118 may be configured to match the performance of feedback path 108. The circuit performance monitor 120 is configured to monitor feedback path information of the one or more replica feedback paths. In some implementations, the replica feedback paths may be placed close to their corresponding feedback paths, for example the replica feedback path 116 may be placed in close proximity with the feedback path 106] the monitor circuit being configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time; [performance data collector 122, [0038]: "...the circuit performance monitor 120 may include a performance data collector 122. The performance data collector 122 may be configured to collect measured performance data of the one or more replica feedback paths, compare the measured performance data to a set of reference performance data, and generate performance differences between the measured performance data and the set of reference performance data based on the comparison.]; and
and a monitor controller [circuit performance controller 202, fig. 2A] configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic codes. [[0040]- [0041] "...the integrated circuit 200 may further include a circuit performance controller 202, which may include one or more performance adjusters 204. According to aspects of the present disclosure, the one or more performance adjusters 204 may be configured to determine one or more adjustment voltage values based at least in part on the feedback path information of the one or more replica feedback paths received from the circuit performance monitor 120, and adjust corresponding supply voltages of the one or more circuit blocks, for example circuit blocks 102 and 104, using the one or more adjustment voltage values measured during operation of the integrated circuit 200."…… "adjust corresponding supply voltages of the one or more circuit blocks..."In some implementations, the one or more performance adjusters 204 may be configured to determine one or more operating frequency values based at least in part on the feedback path information of the one or more replica feedback paths, where the feedback path information includes at least one of performance data or signal quality data of the one or more replica feedback paths, and adjust corresponding operating frequencies of the one or more circuit blocks using the one or more operating frequency values during operation of the integrated circuit....]
Regrading Claim 1 Singh does not teach store the diagnostic codes in a log with a corresponding time stamp.
However, Brien teaches store the diagnostic codes in a log with a corresponding time stamp [col.1, lines 59-65, The datalog is a tool created for each chip which provides the status of an individual flip-flop and the time at which the status of the flip-flop occurred….col.3, lines 10-15, Data scan 21 thus scans the entire chip based on the scan chains and scan elements set up, and produces a datalog. The datalog output from data scan 21 lists the time of the data scan, or clock cycle number, and the status of individual flip-flops. Scanned information that enters the flip-flop and output from the data scan 21 is available from the datalog for the flip-flops located on the scan chain. Col. 4, lines 4-10; the scan pattern is run through data scan 21 which generates a datalog, listing the potentially faulty registers output from the device. Failing register determination step 22 then determines which register, if any, has failed. Creating and using datalog corresponds to storing diagnostic code in a log ]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to create a datalog as taught by Brien to determine a condition of the integrated circuit in Singh’s system .
A person with ordinary skill in the art would have been motivated to combine Singh and Brian to improving the testing time required for IC chips requires isolation of the faults on a chip to as small an area as possible. [Col.1, lines 37-41]
Regrading Claim 2, Brien teaches the monitor controller is configured to store the diagnostic codes in the log with one or more of timing margin code, time stamp, voltage, frequency, and a use case.[col.3, lines 10-15, Data scan 21 thus scans the entire chip based on the scan chains and scan elements set up, and produces a datalog. The datalog output from data scan 21 lists the time of the data scan, or clock cycle number, and the status of individual flip-flops. ]
Regrading Claim 5, Singh teaches the monitor controller is configured to generate a health signal [adjustment voltage values] in response to the diagnostic codes and to send the health signal to a higher layer. [[0040]- [0041] "...the integrated circuit 200 may further include a circuit performance controller 202, which may include one or more performance adjusters 204. According to aspects of the present disclosure, the one or more performance adjusters 204 may be configured to determine one or more adjustment voltage values based at least in part on the feedback path information of the one or more replica feedback paths received from the circuit performance monitor 120, and adjust corresponding supply voltages of the one or more circuit blocks, for example circuit blocks 102 and 104, using the one or more adjustment voltage values measured during operation of the integrated circuit 200]
Regrading Claim 6, Singh teaches the monitor controller is configured to compare [[0038]The performance data collector 122 may be configured to collect measured performance data of the one or more replica feedback paths, compare the measured performance data to a set of reference performance data, and generate performance differences between the measured performance data and the set of reference performance data based on the comparison.]] the health signal to a health threshold [[0044] the circuit parameters of the one or more circuit blocks includes at least one of: threshold voltages of the one or more circuit blocks, power usage of the one or more circuit blocks, electrical impedance of the one or more circuit blocks, operating frequencies of the one or more circuit blocks, or a combination thereof] and to send the health signal to the higher layer in response to the health signal crossing the health threshold. . [[0040]- [0041] "...the integrated circuit 200 may further include a circuit performance controller 202, which may include one or more performance adjusters 204. According to aspects of the present disclosure, the one or more performance adjusters 204 may be configured to determine one or more adjustment voltage values based at least in part on the feedback path information of the one or more replica feedback paths received from the circuit performance monitor 120, and adjust corresponding supply voltages of the one or more circuit blocks, for example circuit blocks 102 and 104, using the one or more adjustment voltage values measured during operation of the integrated circuit 200]
Regrading Claim 8, Brien teaches the log [datalog] to store the diagnostic codes; and an external data port, wherein the log is accessible through the external data port. [Fig.1, item 21, col.3, lines 10-16, the datalog output from data scan 21 lists the time of the data scan]]
Regrading Claim 16, Brien teaches the monitor controller is configured to determine an error condition of the integrated circuit and wherein the user notification indicates that a system associated with the IC is not operational. [col.1, lines 59-65, the datalog is a tool created for each chip which provides the status of an individual flip-flop and the time at which the status of the flip-flop occurred. Once an individual register is determined to be faulty, based on the datalog, that failing register is used as a stop point in a static analyzer. The static analyzer is then employed to provide a fan-in report which indicates all logic paths which lead to the failure]
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Singh (Pub No. US 2019/0286179) in view of Case et al. (Case) (Pub No. US 2015/0039916)
Regrading Claim 20 Singh does not teach receiving a shutdown command in response to the condition of the logic path; and initiating a complete shutdown of one or all systems of the IC.
However, Case teaches: receiving a shutdown command in response to the condition of the logic path; and initiating a complete shutdown of one or all systems of the IC. [[0033] if the active low pulse is too long, an error condition occurs in which PMIC 12 powers off IC 16 (e.g. by placing the SoC power to ground).]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention shutdown the IC of Sing’s system based on condition using Case’s teaching
A person with ordinary skill in the art would have been motivated to combine Sign and Case to prevent catastrophic data loss and hardware damage by stopping operations before they corrupt the file system or damage components.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Singh (Pub No. US 2019/0286179) in view of O’Brien (Brien hereinafter) (Patent NO. US 5,550,841) further in view of Pandey et al. (Pub No. US 2023/0214292)
Regrading Claim 3 the combination of Singh and O’Brien does not teach a second monitor circuit formed in the integrated circuit, the second monitor circuit being configured to generate a second diagnostic code to indicate the conditions of the logic and wherein the monitor controller is configured to aggregate the first diagnostic code and the second diagnostic code
However, Pandey teaches a second monitor circuit formed in the integrated circuit, [Fig.1, item 104] the second monitor circuit being configured to generate a second diagnostic code to indicate the conditions of the logic path [Fault Signal out of Safety monitor 104] and wherein the monitor controller is configured to aggregate the first diagnostic code and the second diagnostic code. [[0026] The error management circuit 120 may, based on the detected fault and on the configuration of the error management circuit 120, aggregate received faults and route such aggregated faults to FCCU 102. FCCU 102 then determines, based on the detected fault and on the configuration of FCCU 102, which action to take in response to the detected fault. For example, in some embodiments, FCCU 102 may generate an interrupt request (e.g., to halt an operation of SoC 100 or to perform an action, such as additional tests), request a reset of SoC 100, or take no action, in response to a particular fault]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to aggregate the fault condition in Singh’s system using Pandey’s teaching.
A person with ordinary skill in the art would have been motivated to combine Sing, Brian and Pandey in order to improve reliability and make the system more efficient.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Singh (Pub No. US 2019/0286179) in view of O’Brien (Brien hereinafter) (Patent NO. US 5,550,841) further in view of Case et al. (Case) (Pub No. US 2015/0039916)
Regrading Claim 10 the combination of Singh and Brian does not teach the monitor controller is configured to receive a shutdown, or reduced functionality command from the external safety management control unit.
However, Case teaches: the monitor controller is configured to receive a shutdown, or reduced functionality command from the external safety management control unit. [[0033] if the active low pulse is too long, an error condition occurs in which PMIC 12 powers off IC 16 (e.g. by placing the SoC power to ground).]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to shut down the IC of Sing’s system based on condition using Case’s teaching
A person with ordinary skill in the art would have been motivated to combine Sign, Brian and Case to prevent catastrophic data loss and hardware damage by stopping operations before they corrupt the file system or damage components.
Claims 12-14 is rejected under 35 U.S.C. 103 as being unpatentable over Singh (Pub No. US 2019/0286179) in view of O’Brien (Brien hereinafter) (Patent NO. US 5,550,841) further in view of Ito (Pub No. US 2020/0213452)
Regrading Claim 12 the combination of Singh and Brien does not teach the monitor controller is configured to generate a user notification in response to the diagnostic code sequence.
However, Ito teaches the monitor controller is configured to generate a user notification in response to the diagnostic code sequence. [[0064] performs malfunction location notification (error notification). For example, the main CPU transmits an error notification to an external apparatus such as the PC or the server via the LANC and the LAN ]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to utilize the error notification of Ito to notify the IC condition in Sign’s system.
A person with ordinary skill in the art would have been motivated to combine Sign, Brian and Ito in order to provide proactive issue detection, faster resolution and improved security.
Regrading Claim 13 Ito Teaches the user notification is an interrupt. [[0064] and [0036], the touch panel controller exchanges an interrupt signal and a control signal with the sub CPU. CPU transmits an error notification ]
Regrading Claim 14 Ito Teaches the user notification is sent to an external display. [[0064] performs malfunction location notification (error notification). For example, the main CPU transmits an error notification to an external apparatus such as the PC or the server via the LANC and the LAN…. the operation unit , by transmitting the information to an external apparatus or displaying the information on the LCD unit ]
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Singh (Pub No. US 2019/0286179) in view of O’Brien (Brien hereinafter) (Patent NO. US 5,550,841) further in view of Ito (Pub No. US 2020/0213452) further in view of TOSHIMITSU et al. (Toshimitsu) (Pub No. US 2010/0218026)
Regrading Claim 15 the combination of Singh, Brian and Ito does not teach user notification is sent through a radio interface to a maintenance facility.
However, Toshimitsu teaches: user notification is sent through a radio interface to a maintenance facility. [[0113] The radio state management unit indicates the condition of the communication through the radio interface to the signal analyzing unit]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use radio interface to communicate with the external apparatus of Ito’s system.
A person with ordinary skill in the art would have been motivated to combine Sign, Brian, Ito and Toshimitsu in order to o provide instant, reliable, long-distance communication without needing wires.
Conclusion
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175