DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/26/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Applicant’s Amendment, filed 03/26/2026 has been entered. Claims 1-12 are pending in the Application.
Response to Arguments
Applicant’s arguments, filed 03/26/2026, with respect to the prior art rejection(s) of the claim(s) have been fully considered. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over de Cesare et al US 20120144172, and in view of Roche US 20010047470.
Regarding claim 1, the Applicant argues that the cited reference fails to teach the newly amended limitation “a pending state… wherein the pending state is entered based on a priority comparison with a higher priority interrupt”. However, the newly cited Roche discloses a pending state for an interrupt is entered based on a priority comparison with another higher priority interrupt (see para 0026, If the microprocessor receives interrupts of a same software priority level or of a lower level, it keeps them pending). Therefore, it would have been obvious to modify the interrupt handling of de Cesare and incorporate comparing interrupt priority of Roche. The motivation for doing so is to provide flexibility when servicing interrupts having different priorities.
Based on the reasoning above, the rejections have been modified to address the newly amended limitations. Please see below for the detailed rejections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over de Cesare et al US 20120144172, and in view of Roche US 20010047470.
Regarding claim 1, de Cesare teaches de Cesare teaches an apparatus for implementing interrupt handling (see figure 1) comprising:
a first processing engine (processor 60A);
a second processing engine (processor 60B); and
a timeout monitoring block (see figure 1 and figure 8, timeout control 142 of interrupt controller 50) coupled to the first processing engine and the second processing engine, wherein the timeout monitoring block is configured to reaffinitize an interrupt affined to the first processing engine to the second processing engine (see para 0032, the interrupt controller 50 may initialize a timeout counter with a corresponding timeout value from the timeout register 58. If the timeout expires without the selected processor responding to the interrupt, the interrupt controller 50 may re-evaluate the interrupt and offer the interrupt to another processor) and to transition the interrupt from a pending state to a reaffinitization state (see para 0073, Other embodiments may clear the routed state at the timeout or at any time the interrupt is offered to another processor e.g. transition between routed/unrouted states).
But de Cesare fails to teach the pending state is entered based on a priority comparison with a higher priority interrupt.
However, Roche teaches the pending state is entered based on a priority comparison with a higher priority interrupt (see para 0026, If the microprocessor receives interrupts of a same software priority level or of a lower level, it keeps them pending).
Therefore, it would have been obvious to modify the interrupt handling of de Cesare and incorporate comparing interrupt priority of Roche.
The motivation for doing so is to provide flexibility when servicing interrupts having different priorities.
Regarding claim 2, de Cesare further teaches an interrupt timer configured to trigger a transition from a pending state to a timeout state of the interrupt (see para 0032, timeout register 58).
Regarding claim 3, de Cesare further teaches the interrupt timer is a component of the timeout monitoring block (see figure 1 and figure 8, timeout register 58 is part of timeout control 142).
Regarding claim 4, de Cesare further teaches a distributor configured to control and to manage the first processing engine and the second processing engine (interrupt controller 50, see para 0027).
Regarding claim 5, de Cesare further teaches the timeout monitoring block is coupled to the distributor via a data interface and a control interface (see figure 8 shown different interfaces from timeout control 142 to components of interrupt controller 50 e.g. data interface/control interface).
Regarding claim 6, de Cesare further teaches the timeout monitoring block resides within the distributor (see figure 1 and figure 8, the timeout control unit 142 resides within interrupt controller 50).
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of de Cesare and Roche as applied to claims above, and further in view of Saidi et al US Patent No. 11,042,494.
Regarding claim 7, the combination of de Cesare and Roche teaches all the features with respect to claim 5 as outlined above.
De Cesare further teaches a first peripheral module coupled to the first processing engine (see figure 1, peripheral 64A).
But the combination of de Cesare and Roche fails to teach the first peripheral module is configured to receive a first private peripheral interrupt (PPI) as a first type of interrupt trigger and a first local peripheral interrupt (LPI) as a second type of interrupt trigger.
However, Saidi teaches a peripheral module is configured to receive a first private peripheral interrupt (PPI) as a first type of interrupt trigger and a first local peripheral interrupt (LPI) as a second type of interrupt trigger (see col 2 ln 1-21, a hardware interrupt generated by a peripheral that is routed to a specific processor core may be referred to as a private peripheral interrupt (PPI) or a locality-specific peripheral interrupt (LPI)).
Therefore, it would have been obvious to modify the peripherals of de Cesare and further incorporate different types of interrupts.
The motivation for doing so is to provide support for different types of interrupts based on the system architecture as taught by Saidi (see col 2 ln 1-21, virtualized computer systems can support different types of interrupts based on the system architecture).
Regarding claim 8, de Cesare further teaches a second peripheral module coupled to the second processing engine (see figure 1, peripheral 64B).
Saidi further teaches the second peripheral module is configured to receive a second private peripheral interrupt (PPI) as a third type of interrupt trigger and a second local peripheral interrupt (LPI) as a fourth type of interrupt trigger (see col 2 ln 1-21, a hardware interrupt generated by a peripheral that is routed to a specific processor core may be referred to as a private peripheral interrupt (PPI) or a locality-specific peripheral interrupt (LPI)).
Regarding claim 9, Saidi further teaches a first CPU interface configured to send a first software generated interrupt (SGI) generated by the first processing engine to the distributor (see col 2 ln 1-21, Software generated interrupts (SGIs) may be generated by a CPU and can be used for inter-process communication. SGIs are generally message based interrupts).
Regarding claim 10, Saidi further teaches the first software generated interrupt (SGI) is subsequently routed by the distributor within an information processing system (see figure 1, interrupt controller 114, see col 5 ln 8-24, The IC 114 may also be configured to receive an SGI generated by a processor core which may be targeted to another processor core).
Regarding claim 11, Saidi further teaches a second CPU interface configured to send a second software generated interrupt (SGI) generated by the second processing engine to the distributor (see col 2 ln 1-21, Software generated interrupts (SGIs) may be generated by a CPU and can be used for inter-process communication. SGIs are generally message based interrupts).
Regarding claim 12, Saidi further teaches the second software generated interrupt (SGI) is subsequently routed by the distributor within an information processing system (see figure 1, interrupt controller 114, see col 5 ln 8-24, The IC 114 may also be configured to receive an SGI generated by a processor core which may be targeted to another processor core).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kimelman et al US 20050177668 discloses interrupt pre-emption and ordering where interrupt priorities are compared
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/PHONG H DANG/Primary Examiner, Art Unit 2184
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