DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Information Disclosure Statement
The IDS’s filed on 10/09/2023 and 12/12/2024 have been considered.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into a practical application, and the claims do not recite significantly more than the judicial exception.
Step 1: Claims 1-8 are directed towards a method and fall within the statutory category of processes; Claims 9-16 are directed towards an apparatus and fall within the statutory category of machines; Claims 17-20 are directed towards a non-transitory computer-readable medium and fall within the statutory category of articles of manufacture.
Therefore, “Are the claims directed to a process, machine, manufacture, or composition of matter?” Yes.
Step 2A Prong 1: Claims 1, 9, and 17 recite limitations of “selecting a first processing unit of a plurality of processing units to process a thread based on a use case associated with the thread and locations of the plurality of processing units within an electronic device” and “allocating the thread to be processed on the first processing unit.” These aforementioned limitations are a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, can be performed by the mind. For example, a person can think and observe, judge and evaluate where to assign a task based on the task type and locations of the resources that will be used for the task.
Therefore, “Are the claims directed to a law of nature, a natural phenomenon, or an abstract idea?” Yes, claims 1, 9, and 17 recite abstract ideas.
Step 2A Prong 2: In claims 1, 9, and 17, the judicial exception is not integrated into a practical application. In particular, claims 9 and 17 recite the following additional elements – “a memory,” “one or more processors coupled to the memory,” and “a non-transitory computer-readable medium.” These aforementioned additional limitations generally link the use of the judicial exception to a particular technological environment or field of use (See MPEP § 2106.05(h)) and do not integrate the judicial exception into a practical application.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application?” No, the additional elements do not integrate the abstract idea into a practical application.
Step 2B: Claims 1, 9, and 17 do not include elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above in Step 2A Prong 2, the additional elements generally link the use of the judicial exception to a particular technological environment or field of use, which do not amount to significantly more than the abstract idea.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception?” No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Therefore, claims 1, 9, and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 2, 10, and 18, they recite an additional element of “wherein the first processing unit is selected based on a proximity of each of the plurality of processing units to a data processing unit associated with the use case.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 2, 10, and 18 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 2, 10, and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 3, 11, and 19, they recite an additional element of “wherein the first processing unit is selected based on the first processing unit being further away from the data processing unit than at least a second processing unit of the plurality of processing units.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 3, 11, and 19 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 3, 11, and 19 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 4, 12, and 20, they recite an additional element of “wherein the first processing unit is selected based on the use case being a gaming use case and based on the first processing unit being farther away from a graphical processing unit (GPU) than at least a second processing unit of the plurality of processing units.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 4, 12, and 20 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 4, 12, and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 5 and 13, they recite an additional element of “wherein the first processing unit is selected based on the use case being a video processing use case and based on the first processing unit being farther away from an image signal processor (ISP) than at least a second processing unit of the plurality of processing units.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 5 and 13 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 5 and 13 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claim 6 and 14, they recite an additional element of “wherein the plurality of processing units comprises a plurality of performance clusters.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 6 and 14 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 6 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 7 and 15, they recite additional abstract ideas of “identifying a type of die including the plurality of processing units” and “identifying a configuration of the die based on the type.” These aforementioned limitations are a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, can be performed by the mind. For example, a person can think and observe, judge and evaluate the types, locations, and configuration of various resources. The claims also recite “wherein the configuration indicates the locations of the plurality of processing units.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 7 and 15 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 7 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 8 and 16, they recite an additional element of “wherein the plurality of processing units are on a system-on-chip (SOC).” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 8 and 16 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 8 and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 8-9, 14, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saeidi et al. (US Pub. No. 2018/0143862 A1 hereinafter Saeidi).
As per claim 1, Saeidi teaches a method for processing scheduling (¶ [0020], “The core scheduler may use any of a multitude of criteria to prioritize cores to receive threads, such as core temperature, capabilities of the core, and the like. In one embodiment, the core scheduler takes into account a temperature reading at another processing unit, such as the GPU, and physical distance on the chip between the measured hot spot of the other processing unit and individual ones of the cores…Of course, other factors may come into account, such as temperature of an individual core itself. The core scheduler assigns threads to an individual core based at least in part on physical distance between that core and the detected hot spot.”), comprising: selecting a first processing unit of a plurality of processing units to process a thread based on a use case associated with the thread and locations of the plurality of processing units within an electronic device (¶ [0029], “For example, the CPU 310 and the GPU 320 may both generate significant heat when a graphics-intensive application is executing. Where these components are placed close together, one may cause the performance of the other to suffer due to the heat it produces during operation. Thus, as shown in FIG. 3, the CPU 310 and the GPU 320 may be placed such that they are far enough from each other that the heat exposure of either component to the other may be reduced. Nevertheless, some processor cores (e.g., Core 2) may be positioned closer to the GPU 320, and thus more affected by heat generated by the GPU than processor cores located farther away (e.g., Core 0).” ¶ [0035], “Continuing with the operational example, the CPU scheduler is tasked with placing a particular processing thread with a CPU core. If the CPU scheduler detects a hot spot that corresponds to either one of the temperature sensors TJ1 or TJ2, the CPU scheduler may then access Table 400, parse the contents to identify the particular temperature sensor associated with the hot spot and determine relative physical placements of the cores with respect to the temperature sensor. The CPU scheduler may further rank the cores based on relative physical distance, ranking Core 0 the highest and Core 2 the lowest with respect to this particular criterion…However, assuming that no other criteria overrule the physical distance from the detected hot spot, the CPU scheduler then assigns the processing thread to Core 0. In some examples, applications are written to execute on two cores of a CPU, and in such an example the CPU scheduler may assign the first processing thread to Core 0 and then assign a processing thread of the same application to Core 3 because Core 3 is the second furthest CPU core.”); and allocating the thread to be processed on the first processing unit (¶ [0045]-[0047], “At action 530, the CPU scheduler determines whether the hot spot is inside or is outside the CPU. For instance, various embodiments may include a table or other data structure associating temperature sensors with processing units. Action 530 may include consulting such table to determine where the hotspot is located. If the hot spot is inside the CPU, then the CPU scheduler proceeds to action 550 by placing the processing thread in a queue of a core selected according to various criteria, such as quiescent current (Iddq), temperatures of respective cores (e.g., by placing a processing thread at a core having a lowest temperature among the various cores), location of core within the CPU itself, and/or the like…Continuing with the example, the CPU scheduler is determining which core(s) of the CPU should receive the processing thread, taking into account a hot spot detected at another processing unit, such as GPU 320. In such an instance, the CPU scheduler may assign the processing thread to a core based at least in part on the core's distance from the hot spot. As shown in the current example, at action 540, the load is assigned to the farthest core(s) from where the hottest temperature is sensed.”).
As per claim 6, Saeidi teaches the method of claim 1. Saeidi also teaches wherein the plurality of processing units comprises a plurality of performance clusters (¶ [0020], “As an application is run in the system, the core scheduler determines cores of the CPU to handle individual ones of the threads. The core scheduler may use any of a multitude of criteria to prioritize cores to receive threads, such as core temperature, capabilities of the core, and the like. In one embodiment, the core scheduler takes into account a temperature reading at another processing unit, such as the GPU, and physical distance on the chip between the measured hot spot of the other processing unit and individual ones of the cores. It is generally assumed in this example that a larger physical distance between an individual core and a hot spot on the other processing unit would correlate with lower thermal effects at that particular core attributable to the hot spot. Of course, other factors may come into account, such as temperature of an individual core itself. The core scheduler assigns threads to an individual core based at least in part on physical distance between that core and the detected hot spot.” See also para. 0026. Examiner Note: Para. 0026 of the specification recites “…threads tend to run on one or more performance cores (e.g., performance clusters) as the central processing unit (CPU) scheduler schedules threads in this manner to reduce power consumption and performance.” Thus, cores and clusters are referring to the same thing. Prior art uses the term core rather than cluster as shown above.).
As per claim 8, Saeidi teaches the method of claim 1. Saeidi also teaches wherein the plurality of processing units are on a system-on-chip (SOC) (¶ [0019], “In one embodiment, an SOC may include a variety of different processing units, such as a CPU, a GPU, a DSP, a modem, and the like.”).
As per claim 9, it is an apparatus claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Saeidi also teaches a memory (¶ [0021], “Continuing with the example, the SOC includes a storage device (e.g., non-volatile memory, such as flash memory) to store a table that relates physical distance of individual cores to a particular hot spot.”) and one or more processors coupled to the memory (¶ [0026], “Of course, the scope of embodiments is not limited to any particular number of cores, as other embodiments may include two cores, eight cores, or any other appropriate number of cores in the CPU 310. SOC 300 further includes other system components, such as a first DSP 340, a second DSP 350, a modem 330, GPU 320…”).
As per claim 14, it is an apparatus claim comprising similar limitations to claim 6, so it is rejected for similar reasons.
As per claim 16, it is an apparatus claim comprising similar limitations to claim 8, so it is rejected for similar reasons.
As per claim 17, it is a non-transitory computer-readable medium claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Saeidi also teaches a non-transitory computer-readable medium having instructions stored thereon (See para. 0010.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5, 10-11, 13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Saeidi.
As per claim 2, Saeidi teaches the method of claim 1. Saeidi also teaches wherein the first processing unit is selected based on a proximity of each of the plurality of processing units to a data processing unit associated with the use case (¶ [0019], “In one embodiment, an SOC may include a variety of different processing units, such as a CPU, a GPU, a DSP, a modem, and the like. Each of the different processing units may include one or more temperature sensors that measure temperature and provide that temperature information to a control system of the chip. For example, the control system of the chip may include one or more algorithms as part of a kernel or even higher up in an operating system stack. One of those algorithms may include a core scheduler, which assigns threads to cores of the CPU.” ¶ [0046], “Continuing with the example, the CPU scheduler is determining which core(s) of the CPU should receive the processing thread, taking into account a hot spot detected at another processing unit, such as GPU 320. In such an instance, the CPU scheduler may assign the processing thread to a core based at least in part on the core's distance from the hot spot. As shown in the current example, at action 540, the load is assigned to the farthest core(s) from where the hottest temperature is sensed.” ¶ [0049], “Method 600 illuminates various aspects of scheduling processing threads, and as such, complements the description above of FIG. 5. Method 600 may be performed by a core scheduling algorithm at a processing unit, such as a CPU, GPU, DSP, or other processing unit that may have multiple cores. An example of a core scheduling algorithm is the CPU scheduler discussed above. Method 600 may be performed as part of a thread rebalancing operation or independently in response to new threads.” See also para. 0053-0054. Examiner Note: One of ordinary skill in the art would have recognized that a data processing unit could also be present in the SOC and that the thread scheduling algorithm described above could apply to a data processing unit.).
As per claim 3, Saeidi teaches the method of claim 2. Saeidi also teaches wherein the first processing unit is selected based on the first processing unit being further away from the data processing unit than at least a second processing unit of the plurality of processing units (¶ [0019], “In one embodiment, an SOC may include a variety of different processing units, such as a CPU, a GPU, a DSP, a modem, and the like. Each of the different processing units may include one or more temperature sensors that measure temperature and provide that temperature information to a control system of the chip. For example, the control system of the chip may include one or more algorithms as part of a kernel or even higher up in an operating system stack. One of those algorithms may include a core scheduler, which assigns threads to cores of the CPU.” ¶ [0046], “Continuing with the example, the CPU scheduler is determining which core(s) of the CPU should receive the processing thread, taking into account a hot spot detected at another processing unit, such as GPU 320. In such an instance, the CPU scheduler may assign the processing thread to a core based at least in part on the core's distance from the hot spot. As shown in the current example, at action 540, the load is assigned to the farthest core(s) from where the hottest temperature is sensed.” ¶ [0049], “Method 600 illuminates various aspects of scheduling processing threads, and as such, complements the description above of FIG. 5. Method 600 may be performed by a core scheduling algorithm at a processing unit, such as a CPU, GPU, DSP, or other processing unit that may have multiple cores. An example of a core scheduling algorithm is the CPU scheduler discussed above.” See also para. 0053-0054. Examiner Note: One of ordinary skill in the art would have recognized that a data processing unit could also be present in the SOC and that the thread scheduling algorithm described above could apply to a data processing unit.).
As per claim 5, Saeidi teaches the method of claim 1. Saeidi also teaches wherein the first processing unit is selected based on the use case being a video processing use case and based on the first processing unit being farther away from an image signal processor (ISP) than at least a second processing unit of the plurality of processing units (¶ [0019], “In one embodiment, an SOC may include a variety of different processing units, such as a CPU, a GPU, a DSP, a modem, and the like. Each of the different processing units may include one or more temperature sensors that measure temperature and provide that temperature information to a control system of the chip. For example, the control system of the chip may include one or more algorithms as part of a kernel or even higher up in an operating system stack. One of those algorithms may include a core scheduler, which assigns threads to cores of the CPU.” ¶ [0029], ““For example, the CPU 310 and the GPU 320 may both generate significant heat when a graphics-intensive application is executing. Where these components are placed close together, one may cause the performance of the other to suffer due to the heat it produces during operation. Thus, as shown in FIG. 3, the CPU 310 and the GPU 320 may be placed such that they are far enough from each other that the heat exposure of either component to the other may be reduced. Nevertheless, some processor cores (e.g., Core 2) may be positioned closer to the GPU 320, and thus more affected by heat generated by the GPU than processor cores located farther away (e.g., Core 0).” ¶ [0046], “Continuing with the example, the CPU scheduler is determining which core(s) of the CPU should receive the processing thread, taking into account a hot spot detected at another processing unit, such as GPU 320. In such an instance, the CPU scheduler may assign the processing thread to a core based at least in part on the core's distance from the hot spot. As shown in the current example, at action 540, the load is assigned to the farthest core(s) from where the hottest temperature is sensed.” ¶ [0049], “Method 600 illuminates various aspects of scheduling processing threads, and as such, complements the description above of FIG. 5. Method 600 may be performed by a core scheduling algorithm at a processing unit, such as a CPU, GPU, DSP, or other processing unit that may have multiple cores. An example of a core scheduling algorithm is the CPU scheduler discussed above.” See also para. 0053-0054. Examiner Note: One of ordinary skill in the art would have recognized that if a digital signal processor (DSP) is supported in the reference an image signal processor (ISP) could also be present in the SOC as an obvious variation and that the thread scheduling algorithm described above could apply to an ISP.).
As per claim 10, it is an apparatus claim comprising similar limitations to claim 2, so it is rejected for similar reasons.
As per claim 11, it is an apparatus claim comprising similar limitations to claim 3, so it is rejected for similar reason.
As per claim 13, it is an apparatus claim comprising similar limitations to claim 5, so it is rejected for similar reasons.
As per claim 18, it is a non-transitory computer-readable medium claim comprising similar limitations to claim 2, so it is rejected for similar reasons.
As per claim 19, it is a non-transitory computer-readable medium claim comprising similar limitations to claim 3, so it is rejected for similar reasons.
Claim(s) 4, 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Saeidi as applied to claims 1, 9, and 17 above, and further in view of Kumar et al. (US Patent No. 10,372,495 B2 hereinafter Kumar *cited in IDS*).
As per claim 4, Saeidi teaches the method of claim 1. Saeidi teaches wherein the first processing unit is selected based on the use case being a graphics intensive use case (¶ [0029], “For example, the CPU 310 and the GPU 320 may both generate significant heat when a graphics-intensive application is executing. Where these components are placed close together, one may cause the performance of the other to suffer due to the heat it produces during operation. Thus, as shown in FIG. 3, the CPU 310 and the GPU 320 may be placed such that they are far enough from each other that the heat exposure of either component to the other may be reduced. Nevertheless, some processor cores (e.g., Core 2) may be positioned closer to the GPU 320, and thus more affected by heat generated by the GPU than processor cores located farther away (e.g., Core 0).”) and based on the first processing unit being farther away from a graphics processing unit (GPU) than at least a second processing unit of the plurality of processing units (¶ [0020], “In one embodiment, the core scheduler takes into account a temperature reading at another processing unit, such as the GPU, and physical distance on the chip between the measured hot spot of the other processing unit and individual ones of the cores. It is generally assumed in this example that a larger physical distance between an individual core and a hot spot on the other processing unit would correlate with lower thermal effects at that particular core attributable to the hot spot.” ¶ [0046], “Continuing with the example, the CPU scheduler is determining which core(s) of the CPU should receive the processing thread, taking into account a hot spot detected at another processing unit, such as GPU 320. In such an instance, the CPU scheduler may assign the processing thread to a core based at least in part on the core's distance from the hot spot. As shown in the current example, at action 540, the load is assigned to the farthest core(s) from where the hottest temperature is sensed.”).
Saeidi does not explicitly teach a gaming use case as the reason for selecting a processing unit.
However, Kumar teaches wherein the first processing unit is selected based on the use case being a gaming use case (Col. 3, lines 34-49, “For example, a particular videogame application may be known by the SOC to have requirements for frequency of operation as well as be known for causing a certain amount of heat dissipation at the GPU and at the CPU cores—this is one example of historical use data. This information may be stored in a table or other memory structure by the SOC. Further, information regarding resource usage may be used to update the information stored in the memory structure. When a user opens the application, the SOC accesses the table from memory and determines an acceptable selection of processing cores within the CPU, and hardware threads within those cores to handle execution of the application.”).
Saeidi and Kumar are considered to be analogous to the claimed invention because they are in the same field of thread scheduling and thermal management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Saeidi with Kumar to arrive at the claimed invention. The motivation to modify Saeidi with the teachings of Kumar is that having knowledge that a gaming application is executing on the system allows the system to schedule threads on processing units farther away from the GPU that is executing the gaming application. This allows the threads to execute without being affected by the heat being produced at the GPU.
As per claim 12, it is an apparatus claim comprising similar limitations to claim 4, so it is rejected for similar reasons.
As per claim 20, it is a non-transitory computer-readable medium claim comprising similar limitations to claim 4, so it is rejected for similar reasons.
Claim(s) 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Saeidi as applied to claims 1 and 9 above, and further in view of Chow et al. (NPL Document - "GPUCalorie: Floorplan Estimation for GPU Thermal Evaluation" hereinafter Chow *cited in IDS*).
As per claim 7, Saeidi teaches the method of claim 1. Saeidi teaches identifying a configuration of the SOC, wherein the configuration indicates the locations of the plurality of processing units (¶ [0034]-[0035], “In one example operation, the CPU scheduler takes into account physical distance from a detected hot spot by consulting a table that includes fields that correlate the temperature sensor associated with the detected hot spot with respective physical distances to the various cores. An example is shown in FIG. 4. Table 400 includes two rows, where each row corresponds to one of the temperature sensors TJ1 and TJ2. Each of the columns correlates the respective temperature sensor with a relative physical distance to a particular one of the cores. For instance, with respect to temperature sensor TJ1, Core 0 is the furthest core, whereas Core 2 is the closest CPU core to that particular temperature sensor…Continuing with the operational example, the CPU scheduler is tasked with placing a particular processing thread with a CPU core. If the CPU scheduler detects a hot spot that corresponds to either one of the temperature sensors TJ1 or TJ2, the CPU scheduler may then access Table 400, parse the contents to identify the particular temperature sensor associated with the hot spot and determine relative physical placements of the cores with respect to the temperature sensor.”).
Saeidi fails to explicitly teach identifying a die type and configuration of the die/SOC based on the type.
However, Chow teaches identifying a die type including the plurality of processing units and identifying a configuration of the die based on the type, wherein the configuration indicates the locations of the plurality of processing units (Pg. 239, section II – “GPUCalorie Floorplan Identification”, “GPUCalorie also provides a floorplan estimator that derives a sub-SM component-level floorplan through microbenchmarking and empirical infrared thermography. Together, these two techniques provide modern thermal floorplans and component level energy estimates of GPU components, enabling thermal evaluation of modern GPUs… We transform the thermal map to identify spatial heat generation [9] (which we call a power map)…In other words, we can identify heat generation from thermal output at steady-state. In order to identify the power sources from the filtered heatmaps, we refer to the 2D steady-state thermal found in [9]. The peaks in the power maps are power sources and the troughs are power sinks (where power output is less than the cooling). Now we are able to derive locations of individual components within the SM.”).
Saeidi and Chow are considered to be analogous to the claimed invention because they are in the same field of thread scheduling and thermal management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Saeidi with the floorplan identification/configuration functionality of Chow to arrive at the claimed invention. The motivation to modify Saeidi with the teachings of Chow is that having knowledge of the configuration of a die allows for proper thermal management of the die because thread scheduling can consider the locations of intense heat-producing components.
As per claim 15, it is an apparatus claim comprising similar limitation to claim 7, so it is rejected for similar reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mavila et al. (US Pub. No. 2014/0344827 A1) teaches taking into consideration the temperature and spatial information of cores when scheduling tasks.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN ROBERT DAKITA EWALD whose telephone number is (703)756-1845. The examiner can normally be reached Monday-Friday: 9:00-5:30 ET.
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/J.D.E./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199