DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla, US PGPub 2022/0083243, in view of Hung, US PGPub 2024/0233783, further in view of Cariello, US PGPub 2020/0333976.
With respect to claim 1, Muchherla teaches a storage device, comprising:
a nonvolatile memory comprising a plurality of user blocks (par. 45, nonvolatile memory 130); and
a controller configured to manage the plurality of user blocks in units of super blocks (par. 45), wherein the controller performs a first program operation in units of super pages of a super block (par. 21- “’Block family’ herein shall refer to a possibly non-contiguous set of memory cells (which can reside in one or more full and/or partial blocks, the latter referred to as ‘partitions’ herein) that have been programmed within a specified time window and a specified temperature window, and thus are expected to exhibit similar or correlated changes in their respective data state metrics. A block family can be made with any granularity, containing only whole codewords, whole pages, whole superpages, or whole superblocks, or any combination of these.”),
Muchherla fails to teach each super block comprises multiple user blocks of the plurality of user blocks and a plurality of super pages, wherein each super page comprises at least one page of each of the multiple user blocks of a respective super block. Hung teaches
each super block comprising multiple user blocks of the plurality of user blocks and a plurality of super pages, wherein each super page comprises at least one page of each of the multiple user blocks of a respective super block (par. 69, the physical blocks being the user blocks of the claim).
Muchherla and Hung fail to teach managing first temperature information, associated with the first program operation, in units of a predetermined number of super pages that is fewer than the plurality of super pages of the super block. Cariello teaches:
manages first temperature information, associated with the first program operation, in units of a predetermined number of super pages that is greater than one super page and fewer than the plurality of super pages of the super block (pars. 47-52, temperature information is determined for each group, and as discussed in par. 47, each group can include combination or sub-combination of memory devices, planes, windows, super blocks, blocks, super pages, pages or memory cells. Any combination of super pages would clearly include the number of super pages that is greater than one super page, and not the entire super block).
It would have been obvious to one of ordinary skill in the art, having the teachings of Muchherla and Hung before him before the earliest effective filing date, to modify the storage device of Muchherla with the storage device of Hung, in order to be able to program a super page quickly, with all the pages in the super page being programmed simultaneously, as taught by Hung in par. 69. Further, it would have been obvious, also having the teachings of Cariello before him before the earliest effective filing date, to modify the storage device of Muchherla and Hung with the storage device of Cariello, in order to store determined statistical measures of temperature information for a group of non-volatile memory cells, such as for use to optimize or improve a storage system operation, e.g., adjusting a read process, threshold voltage, a group on which to perform a memory operation, etc., as taught by Cariello in par. 55.
With respect to claim 2, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 1, further comprising:
a temperature sensor (par. 59); and
a working memory, wherein the controller obtains the first temperature information through the temperature sensor based on the first program operation, matches the obtained first temperature information with identification information of the predetermined number of super pages, and stores the matched first temperature information in the working memory (par. 64 and fig. 5, metadata tables 550).
With respect to claim 3, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 2, wherein: the nonvolatile memory comprises a plurality of reserved blocks replacing a bad block when among the plurality of user blocks, a user block is turned into the bad block; and the controller performs a second program operation on the plurality of reserved blocks in units of pages and manages second temperature information, associated with the second program operation, in units of a predetermined number of pages (par. 64, metadata is maintained for mapping blocks and pages, as well as the temperature information).
With respect to claim 4, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 3, wherein the controller obtains the second temperature information through the temperature sensor based on the second program operation, matches the obtained second temperature information with identification information of the predetermined number of pages, and stores the matched second temperature information in the working memory (par. 64, metadata is maintained for mapping blocks and pages, as well as the temperature information, and par. 59, which discloses the temperature sensor).
With respect to claim 5, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 4, wherein: the controller updates the obtained first or second temperature information in a temperature table loaded into the working memory; and the temperature table comprises a first area, in which temperature information on the plurality of user blocks is managed in units of the super blocks, and a second area, in which temperature information on the plurality of reserved blocks is managed in units of the blocks (par. 64, metadata is maintained for mapping blocks and pages, as well as the temperature information, as shown in fig. 5, metadata tables 550).
With respect to claim 6, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 5, wherein: the first area comprises first sub-temperature tables in which temperature information on user blocks, included in each of the super blocks, is stored in units of the predetermined number of super pages; and the second area comprises second sub-temperature tables in which temperature information on each of the reserved blocks is stored in units of the predetermined number of pages (par. 64, metadata is maintained for mapping blocks and pages, as well as the temperature information, as shown in fig. 5, metadata tables 550).
With respect to claim 7, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 5, wherein the controller is configured to: update the obtained first temperature information in the first area when a location, in which the first program operation is performed, is included in the plurality of user blocks; and update the obtained second temperature information in the second area when a location, in which the second program operation is performed, is included in the plurality of reserved blocks (par. 62, data state metric is updated).
With respect to claim 8, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 5, wherein the controller is configured to: store the temperature table, stored in the working memory, in the nonvolatile memory for an idle time or while power of the storage device is turned off; and load the temperature table, stored in the nonvolatile memory, into the working memory when the power of the storage device is turned on (par. 57, “The local memory 119 can store a number of different items of information or data that will be discussed in more detail, including but not limited to, a block family (BF) start time 522, an active block family (BF) identifier 528, a partition queue 534, cursors 538 associated with the memory device 130, and a set of metadata tables 550. This information and data can be flushed to the memory device 130 (or other non-volatile memory) in response to detection of an imminent loss of power.”).
With respect to claim 9, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 5, wherein the controller performs a read operation based on the temperature table loaded into the working memory (par. 21, read performed based on the tables in memory).
With respect to claim 10, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the storage device of claim 2, wherein:
the nonvolatile memory is a NAND flash memory (par. 38, NAND flash); and
the working memory comprises at least one of a dynamic random access memory (DRAM) or a static random access memory (SRAM) (par. 37, DRAM).
Claims 11-18 are a method that corresponds to claims 1-7 and 9, and are rejected using similar logic.
With respect to claim 19, Muchherla teaches a controller controlling an operation of a nonvolatile memory comprising a plurality of user blocks, the controller comprising:
a working memory (par. 64 and fig. 5, metadata tables 550); and
at least one processor (par. 45) configured to manage the plurality of user blocks in units of super blocks, wherein the at least one processor performs a first program operation in units of super pages of the super blocks (par. 21- “’Block family’ herein shall refer to a possibly non-contiguous set of memory cells (which can reside in one or more full and/or partial blocks, the latter referred to as ‘partitions’ herein) that have been programmed within a specified time window and a specified temperature window, and thus are expected to exhibit similar or correlated changes in their respective data state metrics. A block family can be made with any granularity, containing only whole codewords, whole pages, whole superpages, or whole superblocks, or any combination of these.”),
Muchherla fails to teach each super block comprises multiple user blocks of the plurality of user blocks and a plurality of super pages, wherein each super page comprises at least one page of each of the multiple user blocks of a respective super block. Hung teaches
each super block comprising multiple user blocks of the plurality of user blocks and a plurality of super pages, wherein each super page comprises at least one page of each of the multiple user blocks of a respective super block (par. 69, the physical blocks being the user blocks of the claim).
Muchherla and Hung fail to teach storing first temperature information, associated with the first program operation, in the working memory in units of a predetermined number of super pages that is fewer than the plurality of super pages of the super block. Cariello teaches:
stores first temperature information, associated with the first program operation, in the working memory in units of a predetermined number of super pages that is greater than one super page and fewer than the plurality of super pages of the super block (pars. 47-52, temperature information is determined for each group, and as discussed in par. 47, each group can include combination or sub-combination of memory devices, planes, windows, super blocks, blocks, super pages, pages or memory cells. Any combination of super pages would clearly include the number of super pages that is greater than one super page, and not the entire super block).
It would have been obvious to one of ordinary skill in the art, having the teachings of Muchherla and Hung before him before the earliest effective filing date, to modify the storage device of Muchherla with the storage device of Hung, in order to be able to program a super page quickly, with all the pages in the super page being programmed simultaneously, as taught by Hung in par. 69. Further, it would have been obvious, also having the teachings of Cariello before him before the earliest effective filing date, to modify the storage device of Muchherla and Hung with the storage device of Cariello, in order to store determined statistical measures of temperature information for a group of non-volatile memory cells, such as for use to optimize or improve a storage system operation, e.g., adjusting a read process, threshold voltage, a group on which to perform a memory operation, etc., as taught by Cariello in par. 55.
With respect to claim 20, Muchherla, Hung and Cariello teach all limitations of the parent claim. Muchherla further teaches the controller of claim 19, wherein: the nonvolatile memory comprises a plurality of reserved blocks replacing a bad block when among the plurality of user blocks, a user blocks is turned into the bad block; and the at least one processor performs a second program operation on the plurality of reserved blocks in units of blocks and stores second temperature information, associated with the second program operation, in the working memory in units of a predetermined number of pages (par. 64, metadata is maintained for mapping blocks and pages, as well as the temperature information).
Response to Arguments
Applicant's arguments filed 12/01/2025 have been fully considered but they are not persuasive. Applicant’s arguments on pages 8-10 are directed towards Cariello allegedly failing to teach managing first temperature information, associated with a first program operation, in units of a predetermined number of super pages that is greater than one super page and fewer than the plurality of super pages of the super block, as claimed in independent claim 1, and similarly in independent claims 11 and 19. While the examiner agreed in the interview that the cited section of Cariello did not teach this feature, as the prior rejection cited the portion of the art that associated temperature information with a single super page, par. 47 of Cariello describes that a group can be any combination or sub-combination of super pages. Therefore, Cariello not only teaches that a group can be one super page, but any combination of super pages, which would include an amount greater than one and fewer than all.
Conclusion
Gao et al., US PGPub 2024/0143219 teaches managing super pages as a component of a super block. Rayaprolu et al., US PGPub 2023/0395170 teaches managing temperature information for super pages.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132