Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to patent ineligible subject matter.
To determine if a claim is directed to patent ineligible subject matter, the Court has guided the Office to apply the Alice/Mayo test, which requires:
1. Determining if the claim falls within a statutory category;
2A. Determining if the claim is directed to a patent ineligible judicial exception consisting of a law of nature, a natural phenomenon, or abstract idea; and
2B. If the claim is directed to a judicial exception, determining if the claim recites limitations or elements that amount to significantly more than the judicial exception.
(See MPEP 2106).
Step 2A is a two-prong inquiry, (see MPEP 2106.04(II)(A)). Under the first prong, examiners evaluate whether a law of nature, natural phenomenon, or abstract idea is set forth or described in the claim. Abstract ideas include mathematical concepts, certain methods of organizing human activity, and mental processes, (see MEPEP 2106.04(a)(2)). The second prong is an inquiry into whether the claim integrates a judicial exception into a practical application. MPEP 2106.04(d).
During examination, examiners should apply the same eligibility analysis to all claims regardless of the number of exceptions recited therein. Unless it is clear that a claim recites distinct exceptions, such as a law of nature and an abstract idea, care should be taken not to parse the claim into multiple exceptions, particularly in claims involving abstract ideas. Accordingly, if possible examiners should treat the claim for Prong Two and Step 2B purposes as containing a single judicial exception. See MPEP 2106.04(II)(B).
With respect to claim 1, applying step 1, the preamble of claim 1 claims a method so this claim falls within the statutory category of a process. In order to apply step 2A, a recitation of claim 1 is copied below. The limitations of the claim that describe an abstract idea are bolded.
A cascade-based power dissipation optimization method for an amplification circuit, characterized by comprising:
S1, acquiring a relationship of power dissipation of an amplification circuit to input signal amplitudes and voltage gains by means of statistical analysis; and
S2, designing an optimal cascade strategy for the amplification circuit according to the relationship of the power dissipation of the amplification circuit to the input signal amplitudes and the voltage gains, and adjusting the number of stages of the amplification circuit and a voltage gain of each stage of the amplification circuit so as to minimize total power dissipation of the amplification circuit.
Under step 2A prong one, the only two limitations are describing both a mental process and a mathematical calculation. The mental process is designing a “strategy” based on a mathematical relationship. The mathematical relationship is used in both steps of the claim first acquiring the mathematical relationship “by means of a statistical analysis” and second using the relationship to define the strategy “according to the relationship of the power dissipation of the amplification circuit to the input signal amplitudes and the voltage gains”. Similar limitations have been determined by the courts to be both mental processes and mathematical calculations because such language (i.e., defining, determining, processing, and analyzing) can practically be performed in the human mind. For example:
a claim to "collecting information, analyzing it, and displaying certain results of the collection and analysis," where the data analysis steps are recited at a high level of generality such that they could practically be performed in the human mind, Electric Power Group v. Alstom, S.A., 830 F.3d 1350, 1353-54, 119 USPQ2d 1739, 1741-42 (Fed. Cir. 2016)
An application program interface for extracting and processing information from a diversity of types of hard copy documents – Content Extraction, 776 F.3d at 1345, 113 USPQ2d at 1356.
(see MPEP 2106.04(a)(2)(III)).
Additionally, mathematical relationships are patent ineligible. For example:
a relationship between reaction rate and temperature, which relationship can be expressed in the form of a formula called the Arrhenius equation.
(see MPEP 2106.04(a)(2)(I)(A)).
Under step 2A prong two, the judicial exception has not been integrated into a practical application. Here, the claim recites no additional limitations.
If the claim as a whole integrates the recited judicial exception into a practical application, then it would be patent eligible. Examiner reviewed the specification, and could not find a specific application discussed. The following paragraph describes “a range of applications” of the mathematical model, but those applications are not enumerated:
...it is difficult to establish a universal mathematical model that represents the power dissipation of the amplification circuit. A power dissipation model of an amplification circuit acquired by performing statistical analysis on measurement data of specific circuits is more practical, thereby greatly simplifying modeling processes and expanding the range of applications...
(Specification [page 2 paragraph 5 line 3]-[page 3 paragraph 1 line 3]).
Moving on to step 2B of the analysis, Examiner must consider whether each claim limitation individually or as an ordered combination amounts to significantly more than the abstract idea. This analysis includes determining whether an inventive concept is furnished by an element or a combination of elements that is beyond the judicial exceptions. For limitations that were categorized as “apply it” or generally linking the use of the abstract idea to a particular technological environment or field of use, the analysis is the same. The limitations that were determined to be extra-solution activity will require further analysis.
There are no additional limitations provided in this claim. Therefore, there are no limitations that can be considered “significantly more”. After reviewing the specification and looking at the claim as a whole, there is no indication that this claim is directed to a combination of known elements arranged or organized in an unconventional manner. As drafted and under a broadest reasonable interpretation, generic computer components may be arranged in the conventional manner to perform the claimed limitations. Therefore, looking at the claim as an ordered combination, the limitations do not amount to significantly more than the abstract idea.
For the foregoing reasons, claim 1 is rejected under 35 U.S.C. 101 as being directed to patent ineligible subject matter.
With respect to claim 2, the claimed invention is directed to an abstract idea without significantly more. The claim recites: in step S1, the statistical analysis is performed with respect to the power dissipation of the amplification circuit for different input signal amplitudes and voltage gains, so as to acquire a function expression
P
A
V
i
n
,
G
of the power of dissipation of the amplification circuit in relation to the input signal amplitude and the voltage gain, where G is the voltage gain, and
G
=
A
V
o
u
t
A
V
i
n
,
A
V
i
n
representing the amplitude of an input signal
V
i
n
,
and
A
V
o
u
t
representing the amplitude of an output signal
V
o
u
t
. The limitation is modifying S1 by giving further details on the statistical analysis. In that context, placing further limitations on a mental process and mathematical calculation does not change the nature of the limitation. In this particular limitation, the claim is further claiming a formula, which is a different abstract idea, and therefore patent ineligible for being a judicial exception, (see MPEP 2106.04(a)(2)(I)(B)). This judicial exception is not integrated into a practical application because there are no additional limitations outside of the abstract idea other than what has already been considered. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reason. For the foregoing reasons, claim 2 is rejected under 35 U.S.C. 101, as being directed to patent ineligible subject matter.
With respect to claim 3, the claimed invention is directed to an abstract idea without significantly more. The claim recites: wherein step S2 comprises: performing cascade on the amplification circuit having a total voltage gain of G, so as to acquire a cascade amplification form consisting of n stages of cascaded amplification circuits in which a voltage gain of a stage-i amplification circuit is G_i, wherein
∏
i
=
1
n
G
i
=
G
, i = 1,2,...,n , and n is the number of stages of the amplification circuit, wherein for an amplification circuit of which the number of stages is K, i.e., a K-stage amplification circuit, power dissipation thereof satisfies
P
s
u
m
(
K
)
=
P
A
V
i
n
,
G
1
+
P
A
V
i
n
G
1
,
G
2
+
…
+
P
A
V
i
n
∏
i
=
1
K
-
2
G
i
,
G
K
-
1
+
P
A
V
i
n
∏
i
=
1
K
-
1
G
i
,
G
/
∏
i
=
1
K
-
1
G
i
,
and the voltage gain Gi of each stage of the amplification circuit is adjusted so as to minimize the power dissipation of the k-stage amplification circuit. The limitation is modifying S2 by giving further details on the cascade strategy. In that context, placing further limitations on a mental process and mathematical calculation does not change the nature of the limitation. In this particular limitation, the claim is further claiming a formula, which is a different abstract idea, and therefore patent ineligible for being a judicial exception, (see MPEP 2106.04(a)(2)(I)(B)). This judicial exception is not integrated into a practical application because there are no additional limitations outside of the abstract idea other than what has already been considered. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reason. For the foregoing reasons, claim 3 is rejected under 35 U.S.C. 101, as being directed to patent ineligible subject matter.
With respect to claim 4, the claimed invention is directed to an abstract idea without significantly more. The claim recites: wherein when the K -stage amplification circuit has a given input signal amplitude and a given total voltage gain G and has the minimum power dissipation, that is, when G,,w the voltage gain of each stage of the amplification circuit satisfies:
∂
P
s
u
m
(
K
)
∂
G
i
=
0
where
P
s
u
m
(
K
)
represents the power dissipation of the K -stage amplification circuit, Gi, represents the voltage gain of the stage-i amplification circuit, and i =1, 2, ..., K -1. The limitation is modifying S2 by giving further details on how optimization is performed. In that context, placing further limitations on a mental process and mathematical calculation does not change the nature of the limitation. In this particular limitation, the claim is further claiming a formula, which is a different abstract idea, and therefore patent ineligible for being a judicial exception, (see MPEP 2106.04(a)(2)(I)(B)). This judicial exception is not integrated into a practical application because there are no additional limitations outside of the abstract idea other than what has already been considered. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reason. For the foregoing reasons, claim 4 is rejected under 35 U.S.C. 101, as being directed to patent ineligible subject matter.
With respect to claim 5, the claimed invention is directed to an abstract idea without significantly more. The claim recites: wherein selection of Kmax, which is the optimal number of stages of the amplification circuit, satisfies:
if
P
s
u
m
1
≤
P
s
u
m
2
, then K_max = 1, and
if
P
s
u
m
1
>
P
s
u
m
2
, then K_max satisfies
P
s
u
m
K
m
a
x
<
P
s
u
m
K
m
a
x
-
1
and
P
s
u
m
K
m
a
x
≤
P
s
u
m
K
m
a
x
+
1
where K_max represents the optimal number of stages of the amplification circuit,
P
s
u
m
K
represents the power dissipation of the K -stage amplification circuit, and
P
s
u
m
K
m
a
x
represents the power dissipation of the amplification circuit employing the optimal cascade strategy. The limitation is modifying S2 by giving further details on how optimization is performed. In that context, placing further limitations on a mental process and mathematical calculation does not change the nature of the limitation. In this particular limitation, the claim is further claiming a formula, which is a different abstract idea, and therefore patent ineligible for being a judicial exception, (see MPEP 2106.04(a)(2)(I)(B)). This judicial exception is not integrated into a practical application because there are no additional limitations outside of the abstract idea other than what has already been considered. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reason. For the foregoing reasons, claim 5 is rejected under 35 U.S.C. 101, as being directed to patent ineligible subject matter.
With respect to claim 6, the claimed invention is directed to an abstract idea without significantly more. The claim recites: wherein the power dissipation of the amplification circuit satisfies:
P
A
V
i
n
,
G
=
(
1
-
α
)
-
1
P
e
f
f
e
c
t
A
V
i
n
,
G
wherein
P
A
V
i
n
,
G
represents power dissipation actually used for signal amplification when the input signal amplitude of the amplification circuit is
A
V
i
n
and the voltage gain is G , and
α
is an energy conversion loss coefficient, and represents the ratio of an energy loss not used for signal amplification but lost in the form of heat during signal amplification to the total power dissipation, and the energy conversion loss coefficient increases as the voltage gain increases. The limitation is modifying both S1 and S2 by giving further details on the definition of power dissipation. In that context, placing further limitations on a mental process and mathematical calculation does not change the nature of the limitation. In this particular limitation, the claim is further claiming a formula, which is a different abstract idea, and therefore patent ineligible for being a judicial exception, (see MPEP 2106.04(a)(2)(I)(B)). This judicial exception is not integrated into a practical application because there are no additional limitations outside of the abstract idea other than what has already been considered. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reason. For the foregoing reasons, claim 6 is rejected under 35 U.S.C. 101, as being directed to patent ineligible subject matter.
With respect to claim 7, the claimed invention is directed to an abstract idea without significantly more. The claim recites: A cascade-based power dissipation optimization system for an amplification circuit, characterized by comprising: a computer-readable storage medium and a processor, the computer-readable storage medium being configured to store executable instructions, and the processor being configured to read the executable instructions stored in the computer-readable storage medium, and to perform the cascade-based power dissipation optimization method for an amplification circuit according to claim 1. The claim is directed to a system which is a machine -- a different statutory category than a method. The machine comprises two parts: “a computer readable storage medium” and “a processor”. Under a broadest reasonable interpretation in light of the specification, a computer readable storage medium is a signal, and signals are not patent eligible. Therefore, this limitation cannot cure the deficiencies of the independent claim. A processor provides physical structure, but in this particular case, the processor is an “apply it” limitation (see MPEP 2106.05(f)) because the computer components are being used in their ordinary capacity to perform a mathematical calculation. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reason. For the foregoing reasons, claim 7 is rejected under 35 U.S.C. 101, as being directed to patent ineligible subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Minimum power design of RF front ends” (2004-Baltus) in view of “Fast Offset Compensation for a 10Gbps Limit Amplifier” (2004-Crain)
With respect to claim 1, Baltus teaches A cascade-based power dissipation optimization method for an amplification circuit, characterized by comprising (see section 5.5.1 general problem, [pages 86-87]; and section 5.5.3 general solution [pages 91-92]; FIG. 60 shows cascaded stages and eq. (46) gives the relationships, [page 86]; "An infinite number of solutions exist. To find a unique solution, one more constraint is needed: the solution has to achieve the global minimum value of P_tot", [page 87 paragraph 2 lines 1-2]): S1, acquiring a relationship of power dissipation of an amplification circuit to input signal amplitudes and voltage gains by means of statistical analysis (step 1 is defining the general problem, [pages 86-87]; specifically the equation P_i = kappa_i * G_i * IP3_i in eq. (46), [page 86]; "IP3 is defined as the input power at which the extrapolated third-order output power equals the extrapolated power of the desired signal. This is discussed in more detailed in Section H.2, and the relation between IP3 and the effect of interferers is discussed in more detail in Appendix G", [page 5 paragraph 2 lines 8-11]; Solving IP3_i requires solving for the input signal amplitude, which is a statistical method using extrapolation, see H.2.1. IP3 [page 246-251]; specifically, the figure at [page 247] shows the extrapolation technique; the signal amplitude alpha is first defined at eq. (176), [page 248]; the rest of [page 249] shows how to solve the equation for the intersection between the extrapolated first order and third order distortions, thus solving for all of the variables including alpha); and S2, designing an optimal cascade strategy for the amplification circuit according to the relationship of the power dissipation of the amplification circuit to the input signal amplitudes and the voltage gains (step 2 is solving the general problem of eq. (46) to minimize power as described at [page 86-87]; by solving eq's. (58)-(62), [page 92]; with the inclusion of section H.2.2 in the Appendix for solving for IP3 of all stages, [pages 251-255], which then solves the signal amplitudes alpha in eq's (176) and (178) of section H.2.1, [pages 248-249]), and adjusting the number of stages of the amplification circuit and a voltage gain of each stage of the amplification circuit so as to minimize total power dissipation of the amplification circuit ("In the next step, a minimum power front end can be assembled by applying the OSITs to the original subcircuits with the parameters determined by the solution (58)-(62). This will result in new subcircuits with the optimum gain and linearity for the front end. These new subcircuits can then be assembled into a front end circuit by cascading them according to the selected front end architecture", [page 92 paragraph 1]; OSIT's refer to orthogonal structure independent transforms, which are “adjusting” see [pages 71 and 79]; the reference discusses the cascade transform [page 74], which is adjusting the number of stages, but chooses to specific transforms in the disclosed method, which focus on adjusting IP3, voltage gain, and power dissipation, (see FIGS. 55-56, [page 80-81]), so specifically applying the cascade transform to adjust the number of stages, [page 74], to the main algorithm, [pages 86-92] needs a rationale to combine).
It would have been obvious to one skilled in the art before the effective filing date to combine the main algorithm of Baltus [pages 86-92] with the additional cascade transform Baltus [page 74] because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teachings to arrive at the claimed invention. Baltus discloses a system and method that teaches all of the claimed features, but number of stages is not included as a design variable in the main algorithm. Crain however teaches:
Power dissipation is an important consideration that must considered in the design. If the power dissipation of the final design is too high then the design will not be practical. As mentioned in the previous section, as n increases to the number required to maximize bandwidth, the total gain-bandwidth product also increases. This occurs because the total gain increases faster than the bandwidth decreases. As n continues to increase past the optimum, the gain-bandwidth product decreases. Therefore, for a fixed total gain and bandwidth, the power per stage should also decrease faster than the total power increases as n increases to the optimum. After n exceeds the optimum, the power per stage continues to decrease but the total power starts to increase. Intuitively, there should be some number of stages that provides the minimum power dissipation.
(see Crain [page 58 paragraph 1]).
A person having skill in the art would have a reasonable expectation of successfully reducing power dissipation in the system and method of Baltus by modifying the main algorithm of Baltus (Baltus [pages 86-92]) with the additional transform of changing the number of stages as a possible transform (Baltus [page 74]), which would lead to a curve (such as FIG. 5-3 of Crain [page 59]) that shows the minimum power dissipation as a function of number of stages for each circuit optimized based on voltage gain and IP3 described in Baltus. Therefore, it would have been obvious to combine the main algorithm of Baltus [pages 86-92] with this additional cascade transformation taught by Baltus [page 74] to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 2, Baltus in view of Crain teaches all of claim 1, as noted above. Baltus further teaches in step S1, the statistical analysis is performed with respect to the power dissipation of the amplification circuit for different input signal amplitudes and voltage gains, so as to acquire a function expression
P
A
V
i
n
,
G
of the power of dissipation of the amplification circuit in relation to the input signal amplitude and the voltage gain, where G is the voltage gain, and
G
=
A
V
o
u
t
A
V
i
n
,
A
V
i
n
representing the amplitude of an input signal
V
i
n
,
and
A
V
o
u
t
representing the amplitude of an output signal
V
o
u
t
(step 1 is defining the general problem, [pages 86-87]; specifically the equation P_i = kappa_i * G_i * IP3_i in eq. (46), [page 86]; note the subscript i in the equation meaning different IP3 and voltage gains must be solved for; the full solution is then used in the total power dissipation equation: P_tot = SUM^n_i=1 (P_i), and G_tot [page 46]; "IP3 is defined as the input power at which the extrapolated third-order output power equals the extrapolated power of the desired signal. This is discussed in more detailed in Section H.2, and the relation between IP3 and the effect of interferers is discussed in more detail in Appendix G", [page 5 paragraph 2 lines 8-11]; Solving IP3_i requires solving for the input signal amplitude, which is a statistical method using extrapolation, see H.2.1. IP3 [page 246-251]; specifically, the figure at [page 247] shows the extrapolation technique; the signal amplitude alpha is first defined at eq. (176), [page 248]; the rest of [page 249] shows how to solve the equation for the intersection between the extrapolated first order and third order distortions, thus solving for all of the variables including alpha).
With respect to claim 3, Baltus in view of Crain teaches all of the limitations of claim 2, as noted above. Baltus further teaches wherein step S2 comprises: performing cascade on the amplification circuit having a total voltage gain of G, so as to acquire a cascade amplification form consisting of n stages of cascaded amplification circuits in which a voltage gain of a stage-i amplification circuit is G_i, wherein
∏
i
=
1
n
G
i
=
G
, i = 1,2,...,n , and n is the number of stages of the amplification circuit, wherein for an amplification circuit of which the number of stages is K, i.e., a K-stage amplification circuit, power dissipation thereof satisfies
P
s
u
m
(
K
)
=
P
A
V
i
n
,
G
1
+
P
A
V
i
n
G
1
,
G
2
+
…
+
P
A
V
i
n
∏
i
=
1
K
-
2
G
i
,
G
K
-
1
+
P
A
V
i
n
∏
i
=
1
K
-
1
G
i
,
G
/
∏
i
=
1
K
-
1
G
i
,
and the voltage gain Gi of each stage of the amplification circuit is adjusted so as to minimize the power dissipation of the k-stage amplification circuit (P_tot = SUM^n_i=1 (P_i), [page 46]; this is restated in eq. (56); to get the above equation, simply combine the two equations, noting that IP3 is a function of input amplitude as discussed in Appendix H.2 [pages 246-251], and also noting the conditions in eq. (57), [page 92]).
With respect to claim 4, Baltus in view of Crain teaches all of the limitations of claim 3, as noted above. Baltus further teaches wherein when the K -stage amplification circuit has a given input signal amplitude and a given total voltage gain G and has the minimum power dissipation, that is, when G,,w the voltage gain of each stage of the amplification circuit satisfies:
∂
P
s
u
m
(
K
)
∂
G
i
=
0
where
P
s
u
m
(
K
)
represents the power dissipation of the K -stage amplification circuit, Gi, represents the voltage gain of the stage-i amplification circuit, and i =1, 2, ..., K -1 (The required performance of the total front end is defined by Ftot, Gtot, and IP3tot. Using OSITs, the expressions for cascaded noise factor Ftot, linearity IP3tot, and gain Gtot can be solved for Gi and IP3i. If these parameters have been solved, Pi and Ptot can be calculated as well. An infinite number of solutions exist. To find a unique solution, one more constraint is needed: the solution has to achieve the global minimum value of Ptot, [page 87 paragraph 1 line 2]-[page 82 paragraph 2 line 2]; in math, a global minimum is found by taking the derivative (or partial derivative) with respect to the variable(s) to be minimize and setting that derivative or partial derivative to 0; the idea is well known, but also shown in eq. (50) with respect to IP3, [page 89]; a global minimum of P_diss would satisfy this first order condition with respect to both gain and IP3).
With respect to claim 5, Baltus in view of Crain teaches all of the limitations of claim 3, as noted above. Baltus does not teach wherein selection of Kmax, which is the optimal number of stages of the amplification circuit, satisfies:
if
P
s
u
m
1
≤
P
s
u
m
2
, then K_max = 1, and
if
P
s
u
m
1
>
P
s
u
m
2
, then K_max satisfies
P
s
u
m
K
m
a
x
<
P
s
u
m
K
m
a
x
-
1
and
P
s
u
m
K
m
a
x
≤
P
s
u
m
K
m
a
x
+
1
where K_max represents the optimal number of stages of the amplification circuit,
P
s
u
m
K
represents the power dissipation of the K -stage amplification circuit, and
P
s
u
m
K
m
a
x
represents the power dissipation of the amplification circuit employing the optimal cascade strategy.
However, Crain teaches wherein selection of Kmax, which is the optimal number of stages of the amplification circuit, satisfies:
if
P
s
u
m
1
≤
P
s
u
m
2
, then K_max = 1, and
if
P
s
u
m
1
>
P
s
u
m
2
, then K_max satisfies
P
s
u
m
K
m
a
x
<
P
s
u
m
K
m
a
x
-
1
and
P
s
u
m
K
m
a
x
≤
P
s
u
m
K
m
a
x
+
1
where K_max represents the optimal number of stages of the amplification circuit,
P
s
u
m
K
represents the power dissipation of the K -stage amplification circuit, and
P
s
u
m
K
m
a
x
represents the power dissipation of the amplification circuit employing the optimal cascade strategy (these are the conditions by which a global minimum is satisfied when considering power dissipation and number of stages; Crain teaches how to obtain said global minimum in the section labeled “Optimal Number of Stages for Minimum Power Dissipation”, [page 58 paragraphs 1-2]; and gives a helpful diagram showing that these conditions are satisfied at certain points:
PNG
media_image1.png
440
694
media_image1.png
Greyscale
(Crain [page 59]).
It would have been obvious to one skilled in the art before the effective filing date to combine the main algorithm of Baltus [pages 86-92] with the additional cascade transform Baltus [page 74] because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teachings to arrive at the claimed invention. Baltus discloses a system and method that teaches all of the claimed features, but number of stages is not included as a design variable in the main algorithm. Crain however teaches:
Power dissipation is an important consideration that must considered in the design. If the power dissipation of the final design is too high then the design will not be practical. As mentioned in the previous section, as n increases to the number required to maximize bandwidth, the total gain-bandwidth product also increases. This occurs because the total gain increases faster than the bandwidth decreases. As n continues to increase past the optimum, the gain-bandwidth product decreases. Therefore, for a fixed total gain and bandwidth, the power per stage should also decrease faster than the total power increases as n increases to the optimum. After n exceeds the optimum, the power per stage continues to decrease but the total power starts to increase. Intuitively, there should be some number of stages that provides the minimum power dissipation.
(see Crain [page 58 paragraph 1]).
A person having skill in the art would have a reasonable expectation of successfully reducing power dissipation in the system and method of Baltus by modifying the main algorithm of Baltus (Baltus [pages 86-92]) with the additional transform of changing the number of stages as a possible transform (Baltus [page 74]), which would lead to a curve (such as FIG. 5-3 of Crain [page 59]) that shows the minimum power dissipation as a function of number of stages for each circuit optimized based on voltage gain and IP3 described in Baltus. Therefore, it would have been obvious to combine the main algorithm of Baltus [pages 86-92] with this additional cascade transformation taught by Baltus [page 74] to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 7, Baltus in view Crain teaches all of the limitations of claim 1, as noted above. Baltus further teaches A cascade-based power dissipation optimization system for an amplification circuit, characterized by comprising: a computer-readable storage medium and a processor, the computer-readable storage medium being configured to store executable instructions, and the processor being configured to read the executable instructions stored in the computer-readable storage medium, and to perform the cascade-based power dissipation optimization method for an amplification circuit according to claim 1 (instructions are the straight forward algorithm shown in FIG. 65 running on a small computer, which implement the equations, see [page 99 paragraph 2]; a custom computer program is shown in section 5.7 called “front-end architecture tool”, see specifically [page 102 paragraph 2 line 4]; where a small computer executing the algorithm and custom software at least has memory for the databases, [page 102 paragraph 1 line 1] and a processor for the corresponding editor programs, [page 102 paragraph 1 line 2]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Minimum power design of RF front ends” (2004-Baltus) in view of “Fast Offset Compensation for a 10Gbps Limit Amplifier” (2004-Crain) in further view of “High Efficiency RF and Microwave Solid State Power Amplifiers” (2009-Colantonio)
With respect to claim 6, Baltus in view of Crain teaches all of the limitations of claim 2, as noted above. Baltus in view of Crain do not specifically teach wherein the power dissipation of the amplification circuit satisfies:
P
A
V
i
n
,
G
=
(
1
-
α
)
-
1
P
e
f
f
e
c
t
A
V
i
n
,
G
wherein
P
A
V
i
n
,
G
represents power dissipation actually used for signal amplification when the input signal amplitude of the amplification circuit is
A
V
i
n
and the voltage gain is G , and
α
is an energy conversion loss coefficient, and represents the ratio of an energy loss not used for signal amplification but lost in the form of heat during signal amplification to the total power dissipation, and the energy conversion loss coefficient increases as the voltage gain increases.
However, Colantonio teaches wherein the power dissipation of the amplification circuit satisfies:
P
A
V
i
n
,
G
=
(
1
-
α
)
-
1
P
e
f
f
e
c
t
A
V
i
n
,
G
wherein
P
A
V
i
n
,
G
represents power dissipation actually used for signal amplification when the input signal amplitude of the amplification circuit is
A
V
i
n
and the voltage gain is G , and
α
is an energy conversion loss coefficient, and represents the ratio of an energy loss not used for signal amplification but lost in the form of heat during signal amplification to the total power dissipation, and the energy conversion loss coefficient increases as the voltage gain increases (eq. 1.21, [page 7]).
It would have been obvious to one skilled in the art before the effective filing date to combine Baltus in view of Crain with Colantonio because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Baltus in view of Crain discloses a system and method that teaches all of the claimed features except for how power added efficiency relates to power dissipation. Specifically, Baltus gives the power added efficiency equation as eq. (29), [page 61]; and explains in words the equation:
The law of conservation of energy relates to electronic circuits, and thus to RF circuits, through the relation between power consumed from the power supply and signal inputs, and power delivered to signal outputs. The law of conservation of energy requires that, for any typical RF circuit that only exchanges energy with its environment through electrical signals and through heat dissipation, the sum of the average signal powers delivered at the output terminals is less than, or equal to, the sum of the average signal powers received at the inputs, and the power consumed from the power supply.
(Baltus [page 8 footnote 1]), but Baltus does not give the exact derivation of the equation as claimed. A person having skill in the art would have to use some basic algebra to combine the two concepts. Colantonio is a textbook that shows the basic algebra of how to combine the two concepts. A person having skill in the art would have a reasonable expectation of successfully performing algebra to show how power dissipation must satisfy the law of conservation of energy. Therefore, it would have been obvious to combine Baltus in view of Crain with Colantonio to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 4438354 A (Haque) - A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V.sub.error) is inverted and integrated one time for each integration of the input voltage (V.sub.in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V.sub.out), [Abstract].
“Design of the CMOS inverter‐based amplifier: A quantitative approach” (2019-Sharroush) - The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage‐transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade‐offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed, [Abstract].
“Power Amplifiers and Transmitters for RF and Microwave” (2002-Raab) – see section III on efficiency and as well as discussion of efficiency for different classes of amplifiers in section IV, [page 815-819].
“Power-Bandwidth Trade-Off Analysis of Multi-Stage Inverter-Type Transimpedance Amplifier for Optical Communication” (2017-Hiratsuka) - Abstract—This paper discusses an analytical method for performance estimation of multi-stage transimpedance amplifier (TIA). For high speed and energy efficient optical communication, multi-stage TIA composed of pre-amplifier (PA) and Cherry-Hooper amplifier (CHA) are commonly used. However, it is not clear how to decide design parameters of PA and CHA. Additionally, the number of stages is also a design parameter, [Abstract].
“Distortion in Elementary Transistor Circuits” (1999-Sansen) – eq. (1), FIG. 7, and eq. (8) provide a clear illustration of the relationship between IP3, signal amplitude, V_in, and V_out, [pages 316-318].
“Performance Analysis of Operational Transconductance Amplifier at 180nm Technology” (2016-Bendre) – eq. (1) is V_out=A_v x (V_1-V_2) and eq. (2) is P_D = V_DD * I, [page 272]. These are the basic identities used in the art to analyze a CMOS operational amplifier.
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/D.M./Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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