DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-8, and 14-20is/are rejected under 35 U.S.C. 103 as being unpatentable over Altevogt et al. (US PG Pub No. 2019/0095214 A1), further in view of Le et al. (US PG Pub No. 2008/0072018 A1).
Regarding claim 1, Altevogt teaches an apparatus comprising:
dispatch circuitry configured to receive a sequence of decoded instructions for dispatch to issue circuitry as dispatched instructions, and to identify linear chains of instructions from the sequence of decoded instructions based on inter-instruction dependencies between the sequence of decoded instructions ([0021], wherein “the method further includes tracking the number of any instruction currently assigned to each execution unit of the processor; and using the tracked numbers of any instruction currently assigned to each execution unit of the processor for selecting the execution unit. For example, a first set of instructions dispatched to an execution unit may be defined as the dependent instructions of a dependency chain”), wherein each one of the linear chains comprises a sequentially first instruction and one or more further instructions, each of the one or more further instructions being temporarily ineligible for execution due to a dependence on an immediately preceding one of the sequence of instructions comprised in that one of the linear chains ([0035]); and
wherein the dispatch circuitry is configured, for each linear chain of the linear chains: to dispatch the sequentially first instruction of the linear chain to the issue circuitry ([0034]);
in response to receipt of the chain trigger signal, to dispatch the sequentially next one of the of the one or more further instructions comprised in the linear chain to the issue circuitry ([0037]).
Altevogt does not teach offline storage circuitry configured to store the one or more further instructions comprised in a plurality of the linear chains; and to retain the one or more further instructions of the linear chain in the offline storage circuitry until a chain trigger signal identifying the linear chain is received, the chain trigger signal indicating that a previously dispatched instruction, on which a sequentially next one of the one or more further instructions comprised in the linear chain depends, has satisfied a predefined issuing condition.
Le teaches causing an instruction to wait at the relevant one of issue queues, when an unresolved data dependency is detected, until the issue queue is notified by the relevant execution unit that the previous instruction upon which the instruction is data-dependent have all finished execution ([0027]). When execution of the older instruction(s) has finished, the formerly data-dependent instruction becomes eligible for issue from the issue queue to the execution unit ([0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use offline storage (i.e. issue queue) to store the one or more further instructions comprised in a plurality of the linear chains; and to retain the one or more further instructions of the linear chain in the offline storage circuitry until a chain trigger signal identifying the linear chain is received, the chain trigger signal indicating that a previously dispatched instruction, on which a sequentially next one of the one or more further instructions comprised in the linear chain depends, has satisfied a predefined issuing condition. One would be motivated by the desire to hold instructions in storage until data dependences are resolved such as taught by Le ([0027]).
Regarding claim 2, Le teaches the issue circuitry is responsive to receipt of a dispatched instruction: in response to a determination that one or more operands associated with the dispatched instruction are indicated as ready ([0017]), to mark the dispatched instruction as ready for execution; and in response to a determination that the one or more operands associated with the dispatched instruction are not indicated as ready, to store the dispatched instruction in an issue queue ([0027]).
Regarding claim 6, Le teaches the predefined issuing condition is satisfied when a dispatched instruction comprised in the linear chain is issued for execution ([0027]).
Regarding claim 7, Le teaches wherein for at least a predefined type of dispatched instruction, the predefined issuing condition is considered to be speculatively satisfied when the predefined type of dispatched instruction is marked as ready for execution ([0027]).
Regarding claim 8, Le teaches wherein the dispatch circuitry is configured to, when the sequentially next further instruction is dispatched and when the sequentially next further instruction is dependent only on the previously dispatched instruction, mark the sequentially next further instruction as ready for execution ([0027]).
Regarding claim 14, Altevogt teaches wherein the dispatch circuitry is configured to store the one or more further instructions of each linear chain as a linked list within the offline storage circuitry ([0030]).
Regarding claim 15, Le teaches wherein the offline storage circuitry is arranged as a plurality of discrete queues and the dispatch circuitry is configured to store the one or more further instructions of each linear chain in one of the discrete queues ([0027]).
Regarding claim 16, Altevogt and Le do not teach wherein the dispatch circuitry is responsive to a determination that retaining one or more further instructions of one or the linear chains in the offline storage circuitry would cause a capacity of one of the plurality of discrete queues to be exceeded, to split that linear chain into a plurality of linear chains.
It is old and well known to split data structures into smaller components in storage of such data is to be exceeded. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to split that linear chain into a plurality of linear chains. One would be motivated by the desire to split such data components into smaller components such that they can be saved.
Regarding claim 17, Altevogt teaches a system comprising: the apparatus of claim 1, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board ([0002]).
Regarding claim 18, Altevogt teaches achip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component ([0002]).
Regarding claims 19-20, they are the medium and method claims of claim 1 above. Therefore, they are rejected for the same reasons as claim 1 above.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Altevogt et al. (US PG Pub No. 2019/0095214 A1), in view of Le et al. (US PG Pub No. 2008/0072018 A1)., further in view of Walters et al. (US PG Pub No. 2017/0123803 A1).
Regarding claim 9, Altevogt and Le do not teach wherein the offline storage circuitry is responsive to a flush request, to discard the one or more further instructions comprised in each of the linear chains.
Walters teaches it is old and well known to carry out flush requests by discarding all instructions being handling by the pipeline ([0037]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include the use of a flush request, to discard the one or more further instructions comprised in each of the linear chains. One would be motivated by the desire to reset the state of the pipeline using a single re3quest as taught by Walters ([0037]).
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Altevogt et al. (US PG Pub No. 2019/0095214 A1), in view of Le et al. (US PG Pub No. 2008/0072018 A1)., further in view of Vajapeyam et al. (US PG Pub No. 2003/0126408 A1).
Regarding claim 10, Altevogt and Le do not teach wherein: the dispatch circuitry is configured to identify instructions belonging to each linear chain of instructions by assigning a chain identifier from a pool of chain identifiers to those instructions; and the dispatch circuitry is configured, for each decoded instruction of the sequence of decoded instructions: to determine whether the decoded instruction is dependent on one or more active linear chains of instructions; and when the decoded instruction is dependent on one or more active linear chains, to assign, to the decoded instruction, the chain identifier assigned to one of the one or more active linear chains on which the decoded instruction depends.
Vajapeyam teaches assigning a chain identifier from a pool of chain identifiers to those instructions ([0051]; [0053]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to assign a chain identifier from a pool of chain identifiers to those instructions. One would be motivated by the desire to identifiers for each of the chains to organize such information in table mappings as taught by Vajapeyam ([0051]).
Regarding claim 11, Vajapeyam teaches wherein the dispatch circuitry is configured, when the decoded instruction is dependent on one or more active linear chains, to select the chain identifier assigned to a youngest one of the one or more active linear chains on which the decoded instruction depends ([0051]).
Regarding claim 12, Vajapeyam teaches wherein the dispatch circuitry is configured, when the decoded instruction is not dependent on any active linear chains and when at least one further decoded instruction is dependent on the decoded instruction, to perform a chain identifier assignment procedure comprising: when the pool of chain identifiers comprises an unassigned chain identifier, assigning the unassigned chain identifier to the decoded instruction; and when the pool of chain identifiers comprises no unassigned chain identifiers, to dispatch the decoded instruction to the issue circuitry without assigning a chain identifier ([0051]; [0053]).
Regarding claim 13, Vajapeyam teaches wherein the dispatch circuitry is configured, when the decoded instruction is not dependent on any active linear chains and when at no further decoded instructions are identified as being dependent on the decoded instruction, to dispatch the decoded instruction to the issue circuitry without assigning a chain identifier ([0051]; [0053]).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC C WAI whose telephone number is (571)270-1012. The examiner can normally be reached Monday - Friday 9-5.
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/Eric C Wai/Primary Examiner, Art Unit 2195