DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/10/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The IDS filed 6/27/24 is in partial compliance with the provisions of 37 CFR 1.97. The Taiwanese Office Action and Search report cited in the information disclosure statement filed 6/27/24 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Ryu (US 10714478).
As to claim 1, 12, and 20, Ryu teaches a semiconductor memory device (fig. 12) comprising:
a substrate (100) including a cell area (50) and a peripheral area (60) around the cell area (col. 6:45-53);
a cell area isolation film (102) in the substrate (100) and defining the cell area (50, col. 6:54-57);
a bit-line structure (127c) in the cell area (col. 24:38-40), the bit-line structure including a cell conductive line (120c) and a cell line capping film (125c) on the cell conductive line (col. 13, 30-59);
a cell gate electrode (GE) in the cell area (50) of the substrate (100) and intersecting the cell conductive line (see fig. 5A, col. 7:53-67);
Information storage (DSP) in the cell area (50) of the substrate (100, col. 18:23-29);
a cell interlayer insulating film (155) on the bit-line structure (127c, col. 15:19-29);
a peripheral gate structure (127p) in the peripheral area (60) of the substrate (100), the peripheral gate structure (127p) including a peripheral gate conductive film (112p and/or 120p) and a peripheral capping film (120p and/or 125p) on the peripheral gate conductive film (col. 10:16-26);
a peripheral spacer (135p) on a sidewall of the peripheral gate structure (127p, col. 11:9-13);
an etch stop film (137) on the peripheral spacer (135p) and spaced apart from the peripheral gate structure (127p, col. 11:25-32);
a first peripheral insulating film (140) around the peripheral gate structure (127p) on the substrate (100, col. 11:37-49); and
a peripheral interlayer insulating film (145 and 170) covering the peripheral gate structure (127p), the first peripheral insulating film (140), and the peripheral spacer (135p), the peripheral interlayer insulating film (145 and 170) including a material different from a material of the first peripheral insulating film (140, col. 11-60-65),
wherein the etch stop film (137) does not overlap the peripheral gate structure (127p) in a direction perpendicular to an upper surface of the substrate (100),
wherein the peripheral spacer (135p) is between the etch stop film (137) and the peripheral gate structure (127p), and
wherein an upper surface of the peripheral spacer (135p) is in contact with the peripheral interlayer insulating film (145, fig. 12).
As to claim 2, Ryu further teaches the peripheral gate structure (127p) includes a peripheral capping film (125p) on the peripheral gate conductive film (112p and/or 120p), and an upper surface of the peripheral capping film (125p) is in contact with the peripheral interlayer insulating film (145, col. 10:16-26).
As to claim 3, Ryu further teaches a height (h1, see fig. below) between the upper surface of the substrate (100) and the upper surface of the peripheral capping film (125p) is equal to a height (h2, see annotation of fig. 12 below) between the upper surface of the substrate (100) and the upper surface of the peripheral spacer (135p).
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As to claim 4, Ryu further teaches a height (h3, see fig. above) between the upper surface of the substrate (100) and an uppermost level of the etch stop film (137) is equal to a height (h1) between the upper surface of the substrate (100) and the upper surface of the peripheral capping film (125p).
As to claim 5, Ryu further teaches a thickness of the peripheral interlayer insulating film (145 and 170) is greater than a thickness of the peripheral capping film (125p, fig. 12).
As to claim 6, Ryu further teaches a height (h3) between the upper surface of the substrate (100) and an uppermost level of the etch stop film (137) is equal to a height (h2) between the upper surface of the substrate (100) and the upper surface of the peripheral spacer (135p, see fig. above).
As to claim 7, Ryu further teaches an upper surface of the peripheral gate structure (127p) is in contact with the peripheral interlayer insulating film (145, fig. 12), and an uppermost portion of the peripheral gate structure is the peripheral gate conductive film (120 and 125p).
As to claim 8, Ryu further teaches a height (h1) between the upper surface of the substrate (100) and the upper surface of the peripheral gate structure (127p) is equal to a height (h2) between the upper surface of the substrate (100) and the upper surface of the peripheral spacer (135p, see fig. Above).
As to claim 9, Ryu further teaches a height (h1) between the upper surface of the substrate (100) and the upper surface of the peripheral gate structure (127p) is equal to a height (h3) between the upper surface of the substrate (100) and an uppermost level of the etch stop film (137, see fig. above).
As to claim 10, Ryu further teaches the bit-line structure (127c) includes a cell conductive line (120c), and a cell line capping film (125c) on the cell conductive line (120c), and a thickness of the peripheral gate conductive film (112p and 120p) is greater than a thickness of the cell conductive line (120c, fig. 12).
As to claim 11, Ryu further teaches a width (w1) of the upper surface of the peripheral spacer (135p) in a first direction parallel to the upper surface of the substrate is smaller than a width (w2) of a bottom surface of the peripheral spacer (135p) in the first direction (see annotated figure below).
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As to claim 13, Ryu further teaches a thickness of the cell line capping film (125c) is greater than a thickness of the peripheral capping film (125p, see fig. 12).
As to claim 14, Ryu further teaches a first oxide film (145c) between the cell interlayer insulating film (155) and the cell line capping film (125c, col. 11:60-65).
As to claim 15, Ryu further teaches a second etch stop film (150) between the cell interlayer insulating film (155) and the cell line capping film (125c).
As to claim 17, Ryu further teaches a thickness of the cell interlayer insulating film (155) is greater than a thickness of the cell line capping film (125c, fig. 12).
As to claim 18, Ryu further teaches a width (w1 and w2) of the peripheral spacer decreases as the peripheral spacer extends toward the upper surface of the peripheral spacer (see annotated fig. above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu.
As to claim 16, Ryu does not teach a second oxide film between the peripheral capping film and the peripheral interlayer insulating film. However, multi-layered etch stop films are known in the art and would have been obvious to use so as to have etch protection and diffusion protection. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a multi-layered etch stop layer 150 between the peripheral capping film and the peripheral interlayer insulating film, with one of the films containing silicon oxide, for the reasons stated above.
As to claim 19, Ryu further teaches each of the peripheral capping film (125p) and the peripheral interlayer insulating film (145) includes silicon nitride (col. 9:54-55 and col. 11:64-65), and the first peripheral insulating film (140) includes a silicon oxide-based insulating material (obvious, col. 11:60-65). Silicon oxide and silicon nitride are very commonly used dielectrics in the semiconductor industry that are known to have and are commonly used because they have etch selectivites with respect to each other.
Ryu teaches layer 145 and 140 have etch selectivities with respect to each other and that 145 is a silicon nitride or silicon oxynitride (col. 11:60-65). It is obvious that 140 would be silicon oxide so as to meet the etch selectivity requirement while using industrially tested and accepted materials.
Conclusion
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
3/6/26