DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/10/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 3 recites the limitation "the different metal level" in claim 3. There is insufficient antecedent basis for this limitation in the claim. Assuming the Applicant meant “a different metal level”, it is still unclear what is being claimed. Are the two metal lines on different metal levels from each other or from some other feature (i.e. the contacts)? It appears that the Applicant meant for the metal lines M11-M14 to be on a different level than the contacts C1-C8, which can be seen in figures 17 and 18. In order to advance prosecution, this is what will be assumed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 1-3, 5, 6, 8-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2021/0398593) . As to claim 1 , Song teaches a semiconductor memory device (annotated figs. 3A and 3B below) , comprising: a cell substrate (305 and/or 315) comprising a first side (top) and a second side (bottom) disposed opposite to each other ([0077]) ; a plurality of gate electrodes (WL) sequentially stacked on the first side of the cell substrate and extending in a first direction (x-direction, [0077]) ; first and second channel structures (320, see fig. 3B below) extending in a second direction (z-direction) different from the first direction (x-direction) , penetrating through the plurality of gate electrodes (WL) , and disposed adjacent to each other ([0079], fig. 3B below, they are adjacent in the x-direction) ; a first contact (2412) disposed on the first channel structure (see annotated fig. 24 below, [0188]) ; a first metal line (2412) disposed on the first contact (see fig. 24 below, [0188]) ; a second contact different from the first contact (2412, not shown but obviously also on the second contact) , disposed on the second channel structure ([0188]) ; and a second metal line different from the first metal line (2412, not shown in fig. 24 but shown in fig. 2 and described below) , disposed on the second contact, wherein each of the first and second channel structures (320) comprises: a back gate electrode (323) extending in the second direction ([0082]) ; a gate insulating layer (324) disposed on a side wall of the back gate electrode ([0082]) ; a channel layer (322) disposed on an outer wall of the gate insulating layer ([0079]) ; and a ferroelectric layer (321) disposed on an outer wall of the channel layer ([0080]) , wherein the first contact is electrically connected to the back gate electrode of the first channel structure, and the second contact is electrically connected to the back gate electrode of the second channel structure ([0188]) . Fig. 3A shows a cross section of fig. 3B in the y - direction. As can be seen in the annotation of fig. 3B below, the first and second channel structures are adjacent in the x-direction. It is obvious, if not inherent, that all four of the channel structures shown in fig. 3B are substantially similar. Thus, the two channel structures shown in fig. 3A, adjacent in the y -direction, would also be the same and adjacent if the cross section of fig. 3B would have been in the x -direction instead. Fig. 3A and 3B show the contact to the back gate (340) as being located on the substrate, however fig. 24 shows the contact can also be on the top surface of the channel structure (see annotated fig. 24 below). Thus, a contact and metal line per channel structure is known. Further, fig. 24 shows bit lines 2413 extending in the same direction as metal lines 2412. What is not apparently clear is how the metal line attaches to the contacts. That is, do the first and second contacts share the same metal line or different metal lines? As discussed above, fig. 3B shows four identical channel structures. Fig. 2 shows two bit lines (BL) extending in the y-direction. That is, although one bit line contacts multiple channel structures in the y-direction, there are two different bit line (BL) contacting adjacent channel structures in the x-direction. This configuration is shown in the annotated fig. 3B below (although shown with bit lines instead of metal lines, it is obvious the metal lines would extend in the same direction ) . Thus, there are two adjacent channel structures (whether in the x-direction or the y-direction) that would NOT share the same metal line. The limitation of the channels connected to two different metal lines is met. As to claim 2 , Song further teaches the first and second metal lines (2412) are disposed on the first side of the cell substrate (fig. 24) . As to claim 3 , Song further teaches wherein the first and second metal lines are disposed on different metal level s than the contacts (fig. 24) . As to claims 5 and 6 , Song does not explicitly teach a peripheral circuit element and wiring located above or below the substrate. However, having a peripheral circuit for driving the signals to and from the memory device would have been obvious for controlling the memory (i.e. sending read and erase signals)( [0092]). Placing them on the top or bottom side of the gate electrodes would have been obvious as a matter of optimizing spacing and packaging. As to claim 8 , Song further teaches a bit line (2413) electrically connected to the first channel structure and the second channel structure (see fig. 24 above) , wherein the first channel structure and the second channel structure are adjacent in the first direction and share the bit line (see the discussion of choosing adjacent channels in the x-direction or the y-direction, as discussed in the rejection of claim 1). As to claim 9 , Song further teaches a bit line that is in contact with the first channel structure and the second channel structure (see the discussion of choosing adjacent channels in the x-direction or the y-direction, as discussed in the rejection of claim 1). As to claim 10 , Song teaches a semiconductor memory device (figs. 3A and 3B) , comprising: a cell substrate (305 and/or 315, [0077]) ; a plurality of gate electrodes (WL) sequentially stacked on the cell substrate and extending in a first direction (x-direction, [0077]) ; first and second channel structures ( 320, see annotated figs. 3A and 3B above) extending in a second direction (z-direction) different from the first direction and penetrating the plurality of gate electrodes ([0079]) ; and a bit line (2413) disposed on the plurality of gate electrodes (fig. 24, [01 88]) , wherein the first and second channel structures (320) each include a ferroelectric layer (322) , a channel layer (321) , a gate insulating layer (324) and a back gate electrode (323) , which are sequentially disposed on side walls of the plurality of gate electrodes (fig. 3B, [0079] – [0082]) , and the first channel structure and the second channel structure are adjacent to each other in the first direction and share a bit line (see rejection of claim 1) . As to claim 11 , Song further teaches a voltage is independently applied to the back gate electrode of the first channel structure and the back gate electrode of the second channel structure ([0092]) . As to claim s 12 -16 , Song further teaches the plurality of gate electrodes and the first channel structure constitute a plurality of first memory cells ([0077]) , the plurality of gate electrodes and the second channel structure constitute a plurality of second memory cells ([0077] they are independent strings) . Song also teaches varying voltages along the back gate electrodes while floating or sending ground voltages to the word lines WL in many different configurations ([0089] – [0092] and [0096] – [0107] and figs. 8, 10, and 13). As to claim 1 8 , Song further teaches the channel layer of the first channel structure and the channel layer of the second channel structure are in contact with a lower face of the bit line (fig. 24, the bit line 2412 touches the channel layers) . As to claim 19 , Song teaches a semiconductor memory device (figs. 3A and 3B) , comprising: a cell substrate (305 and/or 315, [0077]) ; a plurality of gate electrodes (WL) sequentially stacked on the cell substrate and extending in a first direction (x-direction, [0077]) ; first and second channel structures (320, see annotated figs. 3A and 3B above) extending in a second direction (z-direction) different from the first direction and penetrating the plurality of gate electrodes ([0079]) ; and a bit line (2413) disposed on the plurality of gate electrodes (fig. 24, [0188]) , wherein the first and second channel structures (320) each include a ferroelectric layer (322) , a channel layer (321) , a gate insulating layer (324) and a back gate electrode (323) , which are sequentially disposed on side walls of the plurality of gate electrodes (fig. 3B, [0079] – [0082]) , and a voltage is independently applied to the back gate electrode of the first channel structure and the back gate electrode of the second channel structure ([0092]) . Song does not explicitly teach the memory device is disposed on a main board with a controller electrically connected to the semiconductor memory device, also disposed on the main board . However, having a memory device on the same motherboard as a controller, where the controller is configured to access and control the memory device, is the definition of a computer and is very well-known in the art. As to claim 20 , see rejection of claims 12-16. Allowable Subject Matter Claims 4, 7, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. As to claim 4 , Song fails to teach the first metal line is disposed between the first side of the cell substrate and the plurality of gate electrodes, and the second metal line is disposed on the plurality of gate electrodes. The metal liens are either above (fig. 24) or below (fig. 3) the gate electrodes, but not both. As to claim 7 , Song fails to teach each of the back gate electrodes of the first and second channel structures comprise a first back gate electrode and a second back gate electrode that are separated from each other. As to claim 1 7 , Song fails to teach the channel layer of the first channel structure and the channel layer of the second channel structure extend along an upper face of the bit line and are in contact with each other. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any response to this Office Action should be faxed to (571) 273-8300 or mailed to: Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Hand-Delivered responses should be brought to: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22313 Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KAREN M KUSUMAKAR whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3520 . The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAREN KUSUMAKAR/ Primary Examiner, Art Unit 2897 3/21/26