Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Elections/Restrictions Applicant’s election without traverse of Group II, claims 1-10 and added new claims 21-30 in the reply filed on 12/22/2025 is acknowledged. Claims 11-20 are canceled. Election was made without traverse in the reply filed on 12/22/2025. Priority Acknowledgement is made of applicant’s claim for priority under 35 U.S.C 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon application CN202310576499X filed in PEOPLE'S REPUBLIC OF CHINA on 05/18/2023. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3 -10 are re jected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 states “ and each of the plurality of contact structures is connected with the gate layer of the same layer as the corresponding gate sacrificial layer in the core area through the gate layer of the same layer as the corresponding gate sacrificial layer in the first area ” which is unclear as to what “ same layer ” is referring to. “A same layer” can mean the same physical continuous layer or a same material or a same thickness. In addition, there is an unclear relationship between the gate sacrificial layer and the gate layer. The phrase “same layer” is ambiguous. Moreover, the phrase does not explain how relationship between gate sacrificial layers and gate layers. In addition, the phrase “ through the gate layer of the same layer ” does not have a clear meaning as to if there is a structural or electrical connection between the gate layer and gate sacrificial layers, thereby, rending the scope of the claim uncertain. Therefore, the correspondence between the gate sacrificial layers in the second area and the gate layers in the core area cannot be determined with reasonable certainty. The claim will be interpreted as a contact structure being connected to the gate sacrificial layers for the purpose of examination. However, due to these ambiguities, a person of ordinary skill in the art at the time of filing the claimed invention cannot determine the exact structure or positional relationship the claim is defining. Thus, clarification is requested. Furthermore, claim 3 recites “a plurality of contact structures,” but later refers to “the contact structure.” It is unclear which contact structure is being referenced as no singular “contact structure” has been previously introduced. Therefore, the claim lacks proper antecedent basis and the scope of the claim is uncertain. Claims 4-10 are rejected as they depend on claim 3 and therefore inherit the same concern. Claim Rejections – 35 USC § 103 The following is a quotation of 35 U.S.C. which forms the basis for all obviousness rejections set forth in this office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 21 are rejected under 35 U.S.C § 103 as being unpatentable over FIG. 1 of Lin et al., US Patent Pub. No. 20220320017A1, hereinafter, “Lin” in view of Tang et al., US Patent Pub. No. 20220384369A1, hereinafter “Tang.” An annotated FIG. 1 of the three-dimensional memory device in Lin is shown below. 1557020 2150110 Interconnection structures 0 0 Interconnection structures 2451100 608965 0 0 2485390 2540 0 0 4639310 605790 0 0 4459605 119380 First sealing ring body 0 0 First sealing ring body 4124960 3559810 Stacked structure 0 0 Stacked structure 4067810 3014980 0 0 Regarding claim 1, Lin teaches A semiconductor device (semiconductor memory device in FIG. 1) , comprising: a stacking structure comprising a memory array area ( top-down view shows memory area in FIG. 1 with memory film #132) and a first sealing area (area consist of sealing ring structure #140 in FIG. 1) ; and at least one of sealing structure in the first sealing area (vertical portion #104 is the sealing structure in the first sealing area in FIG. 1) and surrounding the memory array area ( top-down view shows memory area in FIG. 1 with memory film #132) , 800100 -10179050 First sealing ring area 0 0 First sealing ring area wherein the sealing structure (vertical portions #104in FIG. 1) comprises a sealing ring body (sealing ring structure #140 in FIG. 1) penetrating through the stacking structure (plurality of stacked layers #112 in FIG. 1) and at least two of first dummy interconnection structures (interconnect structures #130 is one shape and there are three other shapes of interconnect structures #130) connected with the sealing ring body (interconnect structures #130 are sealing ring #140 in FIG. 1) . Lin does not directly teach at least two circles of first dummy interconnection structures connected with the sealing ring body because the shape of the sealing ring is depicted rectangularly than a circle. However, Tang teaches at least two circles of first dummy interconnection structures (vias #120 shown in a top-down view in FIG. 1 with a circular shape) connected with the sealing ring body (the sealing ring body is #126 and also described as circular in para [0026]) and at least one circle of sealing structure in the first sealing area (the sealing ring body is #126 and also described as circular in para [0026]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider providing a stacking structure, memory array, sealing structure in the first sealing area comprising a sealing ring body penetrating through the stacking structure, as taught by Lin and the circular shape of the sealing structure and the interconnection structures as taught by Tang . A person of ordinary skill in the art would know to incorporate a circular shape in the sealing ring and interconnection structure because one can easily modify the shape of such a structure to accommodate the same structure arrangements. Since Tang teaches a circular structure, a person of ordinary skill in the art would have been motivated to apply the known circular shape of the interconnection structure and sealing ring in Tang to that of Lin for uniform stress distribution and improved mechanical stability in the sealing area of the memory device. Thus, Tang cures the deficiencies of Lin. Regarding claim 21, Lin teaches a memory system comprising (memory system is a 3D configuration in para [0021]) : a three-dimensional memory comprising a semiconductor device comprising (memory system is a 3D configuration in para [0021]) ; and a controller (transistor #106 in FIG. 1 is a controller) coupled with the three-dimensional memory and configured to control the three-dimensional memory (transistor has a source, drain structure, and channel beneath the stacked structure to control the interconnects and memory array in para [0031] and FIG. 1) , wherein the semiconductor device (semiconductor memory device shown in FIG. 1 of Lin) comprises: a stacking structure comprising a memory array area and a first sealing area ( top-down view shows memory area in FIG. 1 with memory film #132) ; and at least one circle of sealing structure in the first sealing area (vertical portion #104 is the sealing structure in the first sealing area in FIG. 1) and surrounding the memory array area ( top-down view shows memory area in FIG. 1 with memory film #132) , wherein the sealing structure (vertical portions #104in FIG. 1) comprises a sealing ring body (sealing ring structure #140 in FIG. 1) penetrating through the stacking structure (plurality of stacked layers #112 in FIG. 1) and at least two of first dummy interconnection structures connected with the sealing ring body (interconnect structures #130 is one shape and there are three other shapes of interconnect structures #130) connected with the sealing ring body (interconnect structures #130 are sealing ring #140 in FIG. 1) . Lin does not directly teach at least two circles of first dummy interconnection structures connected with the sealing ring body because the shape of the sealing ring is depicted rectangularly than a circle. However, Tang teaches at least two circles of first dummy interconnection structures (vias #120 shown in a top-down view in FIG. 1 with a circular shape) connected with the sealing ring body (the sealing ring body is #126 and also described as circular in para [0026]) and at least one circle of sealing structure in the first sealing area (the sealing ring body is #126 and also described as circular in para [0026]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider providing a memory system with a stacking structure, memory array, sealing structure in the first sealing area comprising a sealing ring body penetrating through the stacking structure, as taught by Lin and the circular shape of the sealing structure and the interconnection structures as taught by Tang . A person of ordinary skill in the art would know to incorporate a circular shape in the sealing ring and interconnection structure because one can easily modify the shape of such a structure to accommodate the same structure arrangements and modifying the sealing ring of Lin to have a circular shape as taught in Tang would be an obvious modification to improve the layout compatibility and stress distribution when the memory system operates . Thus, Tang cures the deficiencies of Lin. Claim 2 is rejected under 35 U.S.C. § 103 as being unpatentable over FIG. 1 of Lin and Tang as applied to claim 1 , and further in view of FIG. 13 of Lin. Regarding claim 2, FIG. 1 of Lin teaches the semiconductor device according to claim 1, further comprising. FIG. 1 of Lin does not teach a peripheral device structure comprising: a device area provided with a peripheral device; and a second sealing area. However, FIG. 3 of Lin does teach a peripheral device structure comprising (memory device #600 in FIG. 13) : a device area provided with a peripheral device (top view of memory device #600 in FIG. 13) ; and a second sealing area (a first portion #1300A, and second portion #1300B is shown with a first sealing ring area #1320 and second sealing ring area #1330) ; and at least two of second dummy interconnection structures (plurality of 3D memory arrays #1304 are the second dummy interconnection structures) in the second sealing area (second portion #1300B) and respectively bonded and connected with the at least two circles of first dummy interconnection structures (plurality of 3D memory arrays #1302 are the first interconnection structures connected through intermetal dielectric IMD #1338) . FIGS. 1 & 13 of Lin does not directly teach at least two circles of second dummy interconnection structures because the shape of the sealing ring is depicted rectangularly than a circle. However, Tang teaches at least two circles of second dummy interconnection structures (vias #120 shown in a top-down view in FIG. 1 with a circular shape) . The circular shape is taught by Tang. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider providing a memory system with a stacking structure, memory array, sealing structure in the first sealing area comprising a sealing ring body penetrating through the stacking structure, as taught by Lin FIG. 1 of Lin and the second sealing ring as taught by FIG. 13 of Lin and the circular shape of the sealing structure and the interconnection structures as taught by Tang. A person of ordinary skill in the art would know to incorporate a circular shape in the sealing ring and interconnection structure because one can easily modify the shape of such a structure to accommodate the same structure arrangements and to include another sealing ring to a memory device as taught by FIG. 13 of Lin. Having multiple or at least one sealing rings as shown in FIG. 13 of Lin and modifying the shape for it to be circular as taught by Tang would be obvious to improve barrier performance of the memory device and protect the semiconductor device components with having multiple sealing rings and ensures stress distribution due to the uniform circular shape of the sealing ring . Thus, Tang cures the deficiencies of Lin in FIG. 1 and FIG. 13 . Allowable Subject Matter Claims 3- 10 and 22-30 contain allowable subject matter. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 3, FIG. 1 of Lin in view of Tang and further in view of FIG. 2 of Lin teaches semiconductor device according to claim 1, wherein the memory array area comprises a core area (FIG. 1 of Lin, a vertical portion #104 consists of a core area that includes the central region with the parallel vertical structures which are memory arrays #120 which consist of memory film #132) and a non-core area (FIG. 1 of Lin, the area outside the memory arrays #120 and memory film #132 which includes wordlines #134) , the stacking structure area (FIG. 1 of Lin, top down view shows memory area in FIG. 1 with memory film #132) comprises a plurality of dielectric layers (FIG. 1 of Lin, a plurality of insulating layers #136 in para [0022]) and a plurality of gate layers (FIG. 1 of Lin, a plurality of horizontal conductive layers which are wordlines #134) alternately stacked in the core area and a first area of the non-core area (FIG. 1 of Lin, both the wordlines #134 and the insulating layers #136 are stacked alternative outside the memory areas #120 and within memory array #120) , and the stacking structure comprises the plurality of dielectric layers (plurality of insulating layers #136 in FIG. 1 of Lin,) and a plurality of gate sacrificial layers (Lin, in FIG. 1 where the wordlines #134 were located a plurality of sacrificial layers were formed in FIG. 2A in step #208 in the formation of the stack in BEOL back end of line processing) alternately stacked in a second area of the non-core area (Lin, between the vertical memory channel #130 and memory film structure #130 there is a first, second, third, fourth, and fifth area with both the wordlines #134 and the insulating layers #136 are stacked alternative outside the memory areas #120 which are the non-core areas of FIG. 1) , and wherein the semiconductor device (semiconductor memory device in FIG. 1 of Lin) further comprises: a plurality of contact structures in the second area (Lin, the wordlines #134 are connected the contact structures in the second area such as metallization levels #110 in the back-end-of-line in FIG. 1) a first interconnection structure (Lin, contact structures #108 in the back-end-of-line structure) in contact with the contact structure (Lin, contact structures #108 is in contact with contact structures in the second area which are metallization levels #110) . However, FIG. 1 of Lin in view of Tang and further in view of Lin does not teach wherein the plurality of contact structures respectively extend to gate sacrificial layers of different layers and each of the plurality of contact structures is connected with the gate layer of the same layer as the corresponding gate sacrificial layer in the core area through the gate layer of the same layer as the corresponding gate sacrificial layer in the first area; and wherein the first interconnection structure is of the same material as the first dummy interconnection structure. The claimed process sequence such as contact structures extend to gate sacrificial layers of different layers and the contact structures being connected with the gate layer and wherein the first interconnection structure is of the same material as the first dummy interconnection structure are not taught by Lin and Tang. The prior art may disclose individual concepts such as a memory array and first sealing area, sealing ring structure, stacking structure, and interconnection structures. However, no references teach the specific structure of contact structures extending to gate sacrificial layers of different layers and the contact structures being connected with the gate layer and the first interconnection structure having the same material as the first dummy interconnection structure. Lin and Tang fail to teach or suggest the entire combination as arranged in the claim and the specific process is not rendered obvious by the cited teachings. Additionally, there was no prior art that one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lin and Tang to reach all of the limitations of the claim. Moreover, the primary reference of Lin does not teach extending the metallization levels #110 to gate sacrificial layers in either FIG. 1 or 13. Additionally, both the cited prior arts do not disclose or suggest having a first interconnection structure being of the same material as first dummy interconnection structure. The material uniformity between the interconnection structures and the contact structures extending through multiple layers across distinct regions of the memory device is not taught. For these reasons, the claimed subject matter as a whole would not have been obvious to one of ordinary skill in the art at the time of filing. Therefore, claim 3 contains allowable subject matter. Dependent claims 4-10 depend directly or indirectly from dependent claim 3 and, thus, further define and/or limit the subject matter recited therein. Therefore, dependent claims 4-10 also contain allowable subject matter. Regarding claim 22, FIG. 1 of Lin teaches a semiconductor device comprising: a first stacking structure (FIG. 1 of Lin, top-down view shows memory area in FIG. 1 with memory film #132) comprising alternating first dielectric layers (a plurality of insulating layers #136 in para [0022]) and gate layers (a plurality of horizontal conductive layers which are wordlines #134) ; a contact structure connected with a first gate layer of the gate layers (Lin, the wordlines #134 are connected the contact structures in the second area such as metallization levels #110 in the back-end-of-line in FIG. 1) ; and a sealing structure (vertical portions #104 in FIG. 1) surrounding the first stacking structure (plurality of stacked layers #112 in FIG. 1) Lin does not teach wherein the contact structure and the sealing structure are formed in a same process . The claimed process sequence such as contact structure and the sealing structure are formed in a same process is not taught by Lin. The prior art may disclose individual concepts such as a memory array and first sealing area, sealing ring structure, stacking structure, and interconnection structures. However, no references teach the specific structure of contact structure and the sealing structure are formed in a same process. Lin fails to teach or suggest the entire combination as arranged in the claim and the specific process is not rendered obvious by the cited teachings. Additionally, there was no prior art that one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lin to reach all of the limitations of the claim. Moreover, the reference of Lin does not teach the formation of the contact structure which are metallization level #110 and the sealing structure #104 with the sealing ring body #140 being formed in the same process. In fact, they are formed distinctively with the metallization and interconnect structures being formed as step #206 and the memory layers and channel layers being formed in the final stages in step #220 and #222 subsequently in FIG. 2 of Lin which provides the process of forming the 3D memory device. For these reasons, the claimed subject matter as a whole would not have been obvious to one of ordinary skill in the art at the time of filing. Therefore, claim 22 contains allowable subject matter. Dependent claims 23-30 depend directly or indirectly from dependent claim 22 and, thus, further define and/or limit the subject matter recited therein. Therefore, dependent claims 23-30 also contain allowable subject matter. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MEHEK AHMED whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)-272-4155 . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEHEK AHMED/ Examiner, Art Unit 2812 /William B Partridge/ Supervisory Patent Examiner, Art Unit 2812