Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Correction to Previous Office Action
The previous action which was mailed on 5/29/2026 is replaced with this office action; the finality of the previous action is withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/3/2026 has been entered.
Response to Amendment
Applicant’s submission filed on 2/3/2026 has been entered. Claims 1-20 remain pending in this application.
Response to Arguments
Applicant's arguments filed 2/3/2026 with regards to the rejections under 35 U.S.C. § 102 have been fully considered but they are not persuasive.
Applicant merely asserts that Matthews does not teach the amended claims 1-20 because “Applicant has amended independent claims 1 and 12 to recite features not disclosed by Matthews” without providing any further supporting statements for said assertion.
Examiner disagrees; replacing the old limitation “store the processing path with a packet descriptor in a learning queue, the learning queue comprising a memory” with the new/modified limitations “store, in a learning queue comprising a memory, at least one of the packet or a packet descriptor prior to the processing path being known” and “associate the processing path with the packet descriptor”, while not entirely taught by the portions of Matthews previously cited, are still taught by Matthews; see revised prior art rejection below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Analysis - 35 USC § 101
Claims 1-20 are NOT rejected under 35 U.S.C. § 101 because the claimed invention is integrated into a practical application where packets that are obtained by an interface connection are routed along a processing path that has been determined and stored by a queueing system.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matthews et al. (US 10,277,518, hereinafter Matthews; see IDS dated 3/13/2024).
Regarding claim 1, Matthews teaches a network processing system [network device 100 – Matthews FIG. 1], comprising:
an interface connection to obtain a packet [ports 110a-110n – Matthews FIG. 1];
one or more packet processing components [packet processor 150a and 150b – Matthews FIG. 1; network device 100 is a computing device comprising any combination of hardware and software configured to implement the various logical components described herein, including components 110-190 – Matthews Col 4 Ln 66 to Col 5 Ln 2] individually connected to a system communication channel [traffic manager 125 – Matthews FIG. 1], the one or more packet processing components individually configured to respectively perform a packet processing operation to the packet, the one or more packet processing components comprising one or more processors (the packet, when received, may be processed by a packet processor, such as a packet processor 150 – Matthews Col 21 Ln 9-11); and
a queueing system connected to the system communication channel [queue manager 140 – Matthews FIG. 1], the queueing system to execute one or more instructions comprising:
determine a processing path of the packet from the interface connection and through the one or more packet processing components (FIG. 3 illustrates an example flow 300 for handling packets using queues within a network device – Matthews Col 20 Ln 55-56; block 360 comprises handling the dequeued packet. The packet may be processed, for instance, by any suitable processing component that is associated with the queue to which the packet was assigned. The processing may involve, for instance, determining where to send the packet next – Matthews Col 22 Ln 57-61); and
store, in a learning queue comprising a memory, at least one of the packet or a packet descriptor (device 100 may store packets 105 in temporary memory structures referred to as buffers 130 while the packets 105 are waiting to be processed – Matthews Col 8 Ln 64-66; as the claim limitations are recited as a list of alternatives, the prior art only needs to disclose one of the listed alternatives, where at least “the packet” is disclosed) prior to the processing path being known (when a node receives a data unit, it typically examines addressing information within the data unit… if the addressing information indicates that the receiving node is not the destination for the data unit, the node may look up… forwarding instructions… in cases where multiple paths to the destination node are possible, the forwarding instructions may include information indicating a suitable approach for selecting one of those paths – Matthews Col 6 Ln 15-32; the path is selected AFTER the data unit is received);
associate the processing path (each identifiable traffic flow or group of traffic flows is assigned its own set of queues 142 to which its packets 105 are respectively assigned – Matthews Col 10 Ln 27-30) with the packet descriptor (queue data 200 may include queue arrangement data 210 that indicates which packets 205 are currently in the queue. Each packet 205 is indicated by a packet identifier, which may be, for example, an address of the packet 205 within a memory (e.g. the buffer address), a packet sequence number, or any other identifying data – Matthews Col 15 Ln 58-63); and
access the learning queue to determine a particular processing path (device 100 may be configured to process a packet 105 in a series of stages 155, each stage involving a different set of one or more packet processors 150… the output of each stage 155 is fed to the input of a next stage 155 in the series, until a concluding stage 155 where output is finally provided to ports 190 – Matthews Col 7 Ln 67 to Col 8 Ln 8) for a second packet (designate a second packet assigned to the particular packet queue… the second packet is at the tail of the particular packet queue – Matthews Col 34 Ln 1-5).
Regarding claim 2, Matthews teaches wherein the interface connection comprises one or more ingress ports, wherein the ingress ports are configured to obtain the packet from one of an Ethernet device, a Wi-Fi device, a data over cable service interface specification (DOCSIS) device, or a passive optical network (PON) device (ports 100/190… may actually correspond to the same physical hardware ports on the network device – Matthews Col 7 Ln 1-3; Ethernet port – Matthews Col 20 Ln 1).
Regarding claim 3, Matthews teaches wherein:
the one or more ingress ports generate the packet descriptor and write the packet descriptor to the packet (a packet processor 150, and/or other components described herein, may be configured to “tag” a packet 105 with labels referred to herein as tags… to signal the packet as being significant for some purpose related to the forwarding logic and/or debugging capabilities of the device – Matthews Col 8 Ln 35-41); and
the queueing system is configured to:
read the packet descriptor and direct the packet to a determined queue at a first time prior to the packet processing operation (a packet 105 may be tagged for a variety of reasons, such as to signal the packet as being significant for some purpose related to the forwarding logic and/or debugging capabilities of the device – Matthews Col 8 Ln 37-41), and
modify the packet descriptor at a second time subsequent to the packet processing operation (for delay tracking purposes, a marker identifier and timestamp for the assigned queue may be created and/or updated at this time – Matthews Col 22 Ln 23-27).
Regarding claim 4, Matthews teaches wherein the queueing system comprises:
the learning queue to store the packet prior to the packet being associated with the processing path (queue data 200 may include queue arrangement data 210 that indicates which packets 205 are currently in the queue. Each packet 205 is indicated by a packet identifier, which may be, for example, an address of the packet 205 within a memory (e.g. the buffer address), a packet sequence number, or any other identifying data – Matthews Col 15 Ln 58-63); and
a computing device to determine the processing path and to transmit a portion of the processing path to the one or more packet processing components (visibility packets may be linked to the visibility queue only (i.e. single path), when generated on account of certain terminal events (e.g. dropping). Or, visibility packets may be duplicated to the visibility queue (i.e. copied or mirrored) such that the original packet follows its normal path, as well as traverses the visibility path – Matthews Col 21 Ln 44-50).
Regarding claim 5, Matthews teaches wherein in response to performing the respective packet processing operation, the one or more packet processing components are individually configured to generate a process result, use the process result and the processing path to determine a subsequent packet processing component, and forward the packet to a subsequent packet processing operation queue (block 360 comprises handling the dequeued packet. The packet may be processed, for instance, by any suitable processing component that is associated with the queue to which the packet was assigned. The processing may involve, for instance, determining where to send the packet next… the packet will typically be assigned to yet another queue for further processing – Matthews Col 22 Ln 57-65).
Regarding claim 6, Matthews teaches wherein the one or more packet processing components individually comprise a packet processing operation queue based on the packet processing operation performed by the one or more packet processing components (block 360 comprises handling the dequeued packet. The packet may be processed, for instance, by any suitable processing component that is associated with the queue to which the packet was assigned. The processing may involve, for instance, determining where to send the packet next… the packet will typically be assigned to yet another queue for further processing – Matthews Col 22 Ln 57-65).
Regarding claim 7, Matthews teaches wherein a first packet processing component that performs a first packet processing operation and a second packet processing component that performs the first packet processing operation obtain a packet from the same packet processing operation queue (the processing may lead to a variety of actions, such as… forwarding the packet to a downstream component… in cases where the packet has been dequeued from a special visibility queue, note that block 395 and block 360 are in fact the same processing, with the packet processor of block 360 being, in essence, the special visibility component – Matthews Col 23 Ln 16-22).
Regarding claim 8, Matthews teaches wherein the queueing system obtains processing statistics of the one or more packet processing components as the one or more packet processing components individually perform the packet processing operation to the packet and additional packets (queue data 200 may further include queue status data 240… 240 may include a variety of state information fields for the queue – Matthews Col 17 Ln 37-46).
Regarding claim 9, Matthews teaches wherein in response to the processing statistics associated with a particular packet processing component of the one or more packet processing components satisfying a utilization threshold, the queueing system reconfigures power to the particular packet processing component (queue manager 140 may be configured to take delay-based actions only if the capability to perform that action is enabled for the queue 142. For instance… 142 may have a flag that, when set, instructs the queue manager 140 to perform the delay-based action when the corresponding threshold is exceeded – Matthews Col 14 Ln 53-59; example of a delay-based action is queue expiration… the queue 142 is then “drained” – Matthews Col 14 Ln 12-16).
Regarding claim 10, Matthews teaches wherein in response to the processing statistics associated with a first packet processing component of the one or more packet processing components satisfying a utilization threshold, the queueing system reconfigures power to a second packet processing component of the one or more packet processing components (queue profile data 230 includes an expiration deadline 231 and a delay deadline 232… 230 may include any number of other thresholds for other delay-based actions – Matthews Col 17 Ln 25-37; queue profiles cover the different packet processors).
Regarding claim 11, Matthews teaches further comprising a user interface (input devices 814… a display 812 – Matthews Col 41 Ln 33-53), wherein in response to a first user input, the queueing system provides the processing statistics to the user interface (a packet 105 may be tagged for a variety of reasons, such as to signal the packet as being significant for some purpose related to the forwarding logic and/or debugging capabilities of the device – Matthews Col 8 Ln 37-41; debugging would display statistics and other debugging information to a troubleshooting user), and in response to a second user input, the queueing system is paused causing the network processing system to halt (the device may drop some or all of the packets within the queue without delivering the packets to their intended destination – Matthews Col 3 Ln 67 to Col 4 Ln 2).
Regarding claim 12, the method comprises the same limitations as the system disclosed in claim 1, with the case being that there are two packet processing components, so the same rejection rationale is applicable.
Regarding claim 13, the method comprises the first portion of the limitations of the system disclosed in claim 4, with the case being that there are two packet processing components, so the same rejection rationale is applicable.
Regarding claim 14, the method comprises the remaining portion of the limitations of the system disclosed in claim 4, with the case being that there are two packet processing components, so the same rejection rationale is applicable.
Regarding claim 15, Matthews teaches further comprising:
directing, by the first packet processing component, the first packet to the second queue of the second packet processing component using the first portion of the processing path (device 100 may be configured to process a packet 105 in a series of stages 155, each stage involving a different set of one or more packet processors 150… the output of each stage 155 is fed to the input of a next stage 155 in the series, until a concluding stage 155 where output is finally provided to ports 190 – Col 7 Ln 67 to Col 8 Ln 8); and
subsequent to the second packet processing operation, directing, by the second packet processing component, the first packet to an egress port using the second portion of the processing path (device 100 may be configured to process a packet 105 in a series of stages 155, each stage involving a different set of one or more packet processors 150… the output of each stage 155 is fed to the input of a next stage 155 in the series, until a concluding stage 155 where output is finally provided to ports 190 – Col 7 Ln 67 to Col 8 Ln 8).
Regarding claim 16, Matthews teaches further comprising:
obtaining, by an ingress port, the first packet (a packet 105 may pass from an ingress port 110 to an ingress stage 155 – Matthews Col 8 Ln 12-16);
assigning the packet descriptor to the first packet (a packet 105 may be tagged for a variety of reasons, such as to signal the packet as being significant for some purpose related to the forwarding logic and/or debugging capabilities of the device – Matthews Col 8 Ln 37-41); and
transmitting the first packet to the queueing system (device 100 may be configured to process a packet 105 in a series of stages 155, each stage involving a different set of one or more packet processors 150… the output of each stage 155 is fed to the input of a next stage 155 in the series, until a concluding stage 155 where output is finally provided to ports 190 – Col 7 Ln 67 to Col 8 Ln 8).
Regarding claim 17, the method comprises the same limitations as the system disclosed in claim 3, so the same rejection rationale is applicable.
Regarding claim 18, the method comprises the same limitations as the system disclosed in claim 9, so the same rejection rationale is applicable.
Regarding claim 19, the method comprises the same limitations as the system disclosed in claim 10, so the same rejection rationale is applicable.
Regarding claim 20, the method comprises the same limitations as the system disclosed in claim 2, so the same rejection rationale is applicable.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John Follansbee whose telephone number 571-272-3964. The examiner can normally be reached Monday to Friday 8:30 AM to 5:00 PM MST, with every other Friday off.
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/JOHN A FOLLANSBEE/Supervisory Patent Examiner, Art Unit 2444
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