Prosecution Insights
Last updated: July 17, 2026
Application No. 18/484,526

CIRCUIT FOR OUTPUT CURRENT REGULATION

Final Rejection §102
Filed
Oct 11, 2023
Examiner
CHEN, SIBIN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Final)
87%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
893 granted / 1031 resolved
+18.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
1046
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
66.6%
+26.6% vs TC avg
§102
28.0%
-12.0% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1031 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu (US 2015/0280486). Regarding claim 1, fig. 1 of Hsu discloses a charger circuit comprising: a first transistor [Q4] coupled between a power input [at Vsys] and a power output [at Vchg]; a second transistor [Q5] coupled between the power input and a battery terminal [at Vbat]; a sensing circuit [1101, 1102] coupled to the battery terminal and having a sensor output; and a control circuit [1103] having an input and an output, the input of the control circuit coupled to the sensor output, the output of the control circuit coupled to a control terminal of the first transistor (via PWM4), the control circuit configurable to set a voltage of the control terminal responsive to a signal indicative of a current at the battery terminal. Regarding claim 3, fig. 1 of Hsu discloses a voltage regulator circuit having a regulator input and a regulator output, wherein the regulator output is coupled to the power input, and the regulator input is coupled to the battery terminal, the second transistor being part of the voltage regulator circuit (voltage is regulated via feedback via 1101). Allowable Subject Matter Claims 10-21, 23, and 24 are allowed. Claims 2 and 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIBIN CHEN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Oct 11, 2023
Application Filed
Apr 02, 2025
Non-Final Rejection mailed — §102
Jun 30, 2025
Response Filed
Oct 29, 2025
Request for Continued Examination
Nov 05, 2025
Response after Non-Final Action
Dec 16, 2025
Non-Final Rejection mailed — §102
Apr 16, 2026
Response Filed
Apr 29, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12671565
DIGITAL QUADRATURE CLOCK FOR LOW JITTER APPLICATIONS
2y 4m to grant Granted Jun 30, 2026
Patent 12665503
LOW NOISE CHARGE PUMP CIRCUIT
2y 10m to grant Granted Jun 23, 2026
Patent 12665504
Fast Detection and Discharge for Charge Pump Controller
2y 1m to grant Granted Jun 23, 2026
Patent 12652024
SUPERCONDUCTING QUANTUM CIRCUIT FOR BOSONIC CODES WITH GALVANIC COUPLING
1y 0m to grant Granted Jun 09, 2026
Patent 12640727
ASYMMETRIC COMMON SOURCE INDUCTANCES TO REDUCE TURN-OFF OVERVOLTAGE IN MOSFETS
2y 1m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.2%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1031 resolved cases by this examiner. Grant probability derived from career allowance rate.

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