Prosecution Insights
Last updated: April 19, 2026
Application No. 18/484,526

CIRCUIT FOR OUTPUT CURRENT REGULATION

Non-Final OA §102§112
Filed
Oct 11, 2023
Examiner
CHEN, SIBIN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
87%
Grant Probability
Favorable
2-3
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
886 granted / 1023 resolved
+18.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
16 currently pending
Career history
1039
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
40.9%
+0.9% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1023 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9, 11-21, 23, and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, it claims that the control circuit [presumably 326, 328, 330, 336, 338, 340] has an input coupled to the battery terminal [VBAT]. However, VBAT is not coupled to the control circuit. The nearest indication of this may be V_ACCL, which is the voltage output of 312, which is proportional to the current through 310. However, V_ACCL is not the battery terminal VBAT, and V_ACCL is not coupled to VBAT since voltage V_ACCL is the voltage indication of current through 310. It is unclear if it should be claimed that the control circuit input is coupled to a current sensor output of 312. Regarding claims 11 and 14, they contain the same issue as described above in claim 1. Regarding claims 2-9, 12, 13, 15-21, 23, and 24 these claims are rejected since they depend on claims above. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2014/0191739). Regarding claim 10, fig. 9 of Kim discloses an apparatus comprising: a first transistor [T9] coupled between a power input [VIN] and a power output [Vout], the first transistor configurable to block a current from the power output to the power input; and a switching voltage regulator coupled between the power input and a battery terminal [Vbat], the switching voltage regulator including: a second transistor [M5] coupled between the power input and a switching terminal [node between M5 and M7], the switching terminal coupled to a battery terminal, the second transistor configurable to block a current from the battery terminal to the power input; and a third transistor [M7] coupled between the switching terminal and a ground terminal. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIBIN CHEN/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Oct 11, 2023
Application Filed
Mar 28, 2025
Non-Final Rejection — §102, §112
Jun 30, 2025
Response Filed
Oct 29, 2025
Request for Continued Examination
Nov 05, 2025
Response after Non-Final Action
Dec 11, 2025
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603645
DISCHARGE CONTROL CIRCUIT
2y 5m to grant Granted Apr 14, 2026
Patent 12592685
FLIP-FLOPS AND INTEGRATED CIRCUITS INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12587181
CLOCK SIGNAL CIRCUITS
2y 5m to grant Granted Mar 24, 2026
Patent 12587175
REDUCED POWER CONSUMPTION COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERATING SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12580555
PHASE INTERPOLATOR AND NON-OVERLAPPING CLOCK GENERATOR
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.1%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 1023 resolved cases by this examiner. Grant probability derived from career allow rate.

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