Prosecution Insights
Last updated: July 17, 2026
Application No. 18/484,973

CAPACITOR INCLUDING ANTIFERROELECTRIC LAYER DISPOSED BETWEEN ELECTRODE LAYER AND SECOND ELECTRODE LAYER, ELECTRIC CIRCUIT, CIRCUIT BOARD, ELECTRONIC APPARATUS, AND POWER STORAGE DEVICE

Final Rejection §103
Filed
Oct 11, 2023
Priority
Apr 15, 2021 — JP 2021-069135 +1 more
Examiner
SINCLAIR, DAVID M
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Panasonic Holdings Corporation
OA Round
3 (Final)
68%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
849 granted / 1247 resolved
At TC average
Strong +20% interview lift
Without
With
+20.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1293
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
78.6%
+38.6% vs TC avg
§102
7.8%
-32.2% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1247 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant's arguments filed 12 February 2026 have been fully considered but they are not persuasive. Applicant argues one of ordinary skill in the art would not have combined Wu and Tan as such a combination would not allow a capacitor structure with parallel combinations of at least two base capacitances as the antiferroelectric material of Tan has a dielectric constant that can decrease as an applied electric field increases and thus is unstable. The examiner disagrees with applicant. Wu discloses the dielectric material can be a high-k dielectric material which are known to have variations based on electric field and other environmental factors such as temperature. The dielectric constant K may vary; however, the variation would be across the at least two difference capacitance (i.e. the K in both capacitance areas would be the same), and thus two difference capacitances values would be obtained based on the distance between electrodes. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (such as in high voltage and high temperature environments) as a matter of obvious design choice. Applicant further argues there is no motivation to combine Laibowitz with Tan. The examiner disagrees a clear motivation was provided in the rejection. Specifically, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the dielectric of Tan ‘913 as the dielectric of Wu ‘335 to obtain a capacitor wherein the dielectric has a high dielectric constant and high energy storage capabilities with ease of processing as well as with improved mechanical properties. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Furthermore, the examiner notes it is well within the knowledge of one of ordinary skill in the capacitor art that a dielectric layer can be formed of an antiferroelectric material or a ferroelectric material (i.e. said materials can be substituted for one another). Lastly, applicant argues the examiner has stated that HfO2 is antiferroelectric without providing evidence. The examiner disagrees with said assertion. The only instance in the rejection where that HfO2 is stated to be antiferroelectric is in references to Ali which explicitly discloses an antiferroelectric HfO2. All claims stand rejected. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-10, 12-17, & 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2011/0019335) in view of Tan et al. (US 2007/0117913). In regards to claim 1, Wu ‘335 discloses a capacitor comprising: a first electrode layer (10 – fig. 1a; [0028]); a second electrode layer (20 – fig. 1a; [0028]); and a dielectric layer (15 – fig. 1a; [0028]) disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, wherein an inner portion of the first electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the first electrode layer when the first electrode layer is viewed in plan (fig. 1), an inner portion of the second electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the second electrode layer when the second electrode layer is viewed in plan (fig. 1), and the dielectric layer has a thickness differing from one point to another (fig. 1a). Wu ‘335 fails to disclose the dielectric is an antiferroelectric. Tan ‘913 discloses an antiferroelectric dielectric (abstract). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the dielectric of Tan ‘913 as the dielectric of Wu ‘335 to obtain a capacitor wherein the dielectric has a high dielectric constant and high energy storage capabilities with ease of processing as well as with improved mechanical properties. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In regards to claim 2, Wu ‘335 as modified by Tan ‘913 discloses all the claimed limitations discussed above with respect to claim 1, except for wherein the antiferroelectric layer has a thickness of 10 nanometers or more and 1 micrometer or less. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Tan ‘913 such that the antiferroelectric layer has a thickness of 10 nanometers or more and 1 micrometer or less to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 3, Wu ‘335 as modified by Tan ‘913 discloses all the claimed limitations discussed above with respect to claim 1, except for a ratio of a maximum of the thickness of the antiferroelectric layer to a minimum of the thickness of the antiferroelectric layer is more than 1 and less than 10. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Tan ‘913 such that a ratio of a maximum of the thickness of the antiferroelectric layer to a minimum of the thickness of the antiferroelectric layer is more than 1 and less than 10to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 4, Wu ‘335 as modified by Tan ‘913 discloses all the claimed limitations discussed above with respect to claim 1, except for wherein a maximum of the thickness of the antiferroelectric layer is 500 nanometers or less. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Tan ‘913 such that a maximum of the thickness of the antiferroelectric layer is 500 nanometers or less to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 5, Wu ‘335 as modified by Tan ‘913 discloses all the claimed limitations discussed above with respect to claim 1, except for wherein the thickness of the antiferroelectric layer is smaller than a thickness of the first electrode layer. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Tan ‘913 such that the thickness of the antiferroelectric layer is smaller than a thickness of the first electrode layer to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 6, Wu ‘335 as modified by Tan ‘913 discloses all the claimed limitations discussed above with respect to claim 1, except for wherein the thickness of the antiferroelectric layer is smaller than a thickness of the second electrode layer. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Tan ‘913 such that the thickness of the antiferroelectric layer is smaller than a thickness of the second electrode layer to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 7, Wu ‘335 as modified by Tan ‘913 further discloses wherein the thickness of the antiferroelectric layer varies continuously or stepwise in a particular in-plane direction (fig. 1a of Wu ‘335). In regards to claim 8, Wu ‘335 as modified by Tan ‘913 further discloses wherein the thickness of the antiferroelectric layer varies continuously or stepwise from one end to the other end in a particular in- plane direction (fig. 1a of Wu ‘335). In regards to claim 9, Wu ‘335 as modified by Tan ‘913 further discloses wherein the antiferroelectric layer includes a first region and a second region, the first region having a minimum thickness and having a given area in plan view, the second region having a maximum thickness and having a given area in plan view, and a ratio of the area of the second region in plan view to the area of the first region in plan view is more than 1 and less than 10 (fig. 1a of Wu ‘335 wherein the ratio is 2:3). In regards to claim 10, Wu ‘335 as modified by Tan ‘913 further discloses wherein the antiferroelectric layer includes a connecting portion between a pair of regions having different thicknesses, the connecting portion defining a step corresponding to a difference between the thicknesses of the pair of regions (fig. 1a of Wu ‘335). In regards to claim 12, Wu ‘335 as modified by Tan ‘913 further discloses wherein the antiferroelectric layer includes a plurality of particular regions each having a particular thickness and having a given area in plan view, and the particular regions are disposed apart from each other when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 13, Wu ‘335 as modified by Tan ‘913 further discloses wherein the particular regions are disposed regularly when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 14, Wu ‘335 as modified by Tan ‘913 further discloses wherein each of the particular regions is in a shape of a belt parallel to another belt when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 15, Wu ‘335 as modified by Tan ‘913 further discloses wherein each of the particular regions is in a circular or rectangular shape when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 16, Wu ‘335 as modified by Tan ‘913 further discloses wherein the antiferroelectric layer includes a metal oxide including at least one of hafnium and zirconium ([0029] of Tan ‘913). In regards to claim 17, Wu ‘335 as modified by Tan ‘913 further discloses further comprising a support, wherein the first electrode layer is disposed between the support and the antiferroelectric layer in the thickness direction of the first electrode layer ([0039] of Wu ‘335). In regards to claim 19, Wu ‘335 as modified by Tan ‘913 further discloses an electrical circuit comprising the capacitor according to claim 1 (see claim 1 rejection above) wherein the capacitor is mounted to the electrical circuit ([0052] of Wu ‘335). In regards to claim 20, Wu ‘335 as modified by Tan ‘913 further discloses a circuit board comprising the capacitor according to claim 1 (see claim 1 rejection above), wherein the capacitor is mounted to an electrical circuit formed on the circuit board ([0052] & [0005] of Wu ‘335). In regards to claim 21, Wu ‘335 as modified by Tan ‘913 further discloses an electronic device comprising the capacitor according to claim 1 (see claim 1 rejection above), wherein the capacitor is mounted to an electrical circuit on a circuit board, and the electronic device is equipped with the circuit board ([0052] & [0005] of Wu ‘335). In regards to claim 22, Wu ‘335 discloses an electricity storage device comprising: a battery ([0070] – it is noted cell phones have a battery); and a capacitor, the capacitor comprising: a first electrode layer (10 – fig. 1a; [0028]); a second electrode layer (20 – fig. 1a; [0028]); and a dielectric layer (15 – fig. 1a; [0028]) disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, wherein an inner portion of the first electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the first electrode layer when the first electrode layer is viewed in plan (fig. 1), an inner portion of the second electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the second electrode layer when the second electrode layer is viewed in plan (fig. 1), and the dielectric layer has a thickness differing from one point to another (fig. 1a). Wu ‘335 fails to disclose the dielectric is an antiferroelectric. Tan ‘913 discloses an antiferroelectric dielectric (abstract). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the dielectric of Tan ‘913 as the dielectric of Wu ‘335 to obtain a capacitor wherein the dielectric has a high dielectric constant and high energy storage capabilities with ease of processing as well as with improved mechanical properties. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claim(s) 1-10, 12-17, & 19-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu ‘335 in view of Silicon-doped hafnium oxide anti-ferroelectric thin films for energy storage hereafter referred to as Ali. In regards to claim 1, Wu ‘335 discloses a capacitor comprising: a first electrode layer (10 – fig. 1a; [0028]); a second electrode layer (20 – fig. 1a; [0028]); and a dielectric layer (15 – fig. 1a; [0028]) disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, wherein an inner portion of the first electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the first electrode layer when the first electrode layer is viewed in plan (fig. 1), an inner portion of the second electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the second electrode layer when the second electrode layer is viewed in plan (fig. 1), and the dielectric layer has a thickness differing from one point to another (fig. 1a). Wu ‘335 fails to disclose the dielectric is an antiferroelectric. Ali discloses an antiferroelectric dielectric for use in capacitors (abstract). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the dielectric of Ali as the dielectric of Wu ‘335 to obtain a capacitor wherein the dielectric has high energy storage capabilities. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In regards to claim 2, Wu ‘335 as modified by Ali discloses all the claimed limitations discussed above with respect to claim 1, except for wherein the antiferroelectric layer has a thickness of 10 nanometers or more and 1 micrometer or less. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Ali such that the antiferroelectric layer has a thickness of 10 nanometers or more and 1 micrometer or less to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 3, Wu ‘335 as modified by Ali discloses all the claimed limitations discussed above with respect to claim 1, except for a ratio of a maximum of the thickness of the antiferroelectric layer to a minimum of the thickness of the antiferroelectric layer is more than 1 and less than 10. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Ali such that a ratio of a maximum of the thickness of the antiferroelectric layer to a minimum of the thickness of the antiferroelectric layer is more than 1 and less than 10to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 4, Wu ‘335 as modified by Ali discloses all the claimed limitations discussed above with respect to claim 1, except for wherein a maximum of the thickness of the antiferroelectric layer is 500 nanometers or less. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Ali such that a maximum of the thickness of the antiferroelectric layer is 500 nanometers or less to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 5, Wu ‘335 as modified by Ali discloses all the claimed limitations discussed above with respect to claim 1, except for wherein the thickness of the antiferroelectric layer is smaller than a thickness of the first electrode layer. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Ali such that the thickness of the antiferroelectric layer is smaller than a thickness of the first electrode layer to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 6, Wu ‘335 as modified by Ali discloses all the claimed limitations discussed above with respect to claim 1, except for wherein the thickness of the antiferroelectric layer is smaller than a thickness of the second electrode layer. However, the thickness of a dielectric layer in a capacitor is a result effective variable based on the formula of capacitance, particularly for controlling capacitance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wu ‘335 as modified by Ali such that the thickness of the antiferroelectric layer is smaller than a thickness of the second electrode layer to obtain a desired capacitance. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 7, Wu ‘335 as modified by Ali further discloses wherein the thickness of the antiferroelectric layer varies continuously or stepwise in a particular in-plane direction (fig. 1a of Wu ‘335). In regards to claim 8, Wu ‘335 as modified by Ali further discloses wherein the thickness of the antiferroelectric layer varies continuously or stepwise from one end to the other end in a particular in- plane direction (fig. 1a of Wu ‘335). In regards to claim 9, Wu ‘335 as modified by Ali further discloses wherein the antiferroelectric layer includes a first region and a second region, the first region having a minimum thickness and having a given area in plan view, the second region having a maximum thickness and having a given area in plan view, and a ratio of the area of the second region in plan view to the area of the first region in plan view is more than 1 and less than 10 (fig. 1a of Wu ‘335 wherein the ratio is 2:3). In regards to claim 10, Wu ‘335 as modified by Ali further discloses wherein the antiferroelectric layer includes a connecting portion between a pair of regions having different thicknesses, the connecting portion defining a step corresponding to a difference between the thicknesses of the pair of regions (fig. 1a of Wu ‘335). In regards to claim 12, Wu ‘335 as modified by Ali further discloses wherein the antiferroelectric layer includes a plurality of particular regions each having a particular thickness and having a given area in plan view, and the particular regions are disposed apart from each other when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 13, Wu ‘335 as modified by Ali further discloses wherein the particular regions are disposed regularly when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 14, Wu ‘335 as modified by Ali further discloses wherein each of the particular regions is in a shape of a belt parallel to another belt when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 15, Wu ‘335 as modified by Ali further discloses wherein each of the particular regions is in a circular or rectangular shape when the antiferroelectric layer is viewed in plan from the second electrode layer (fig. 1a of Wu ‘335). In regards to claim 16, Wu ‘335 as modified by Ali further discloses wherein the antiferroelectric layer includes a metal oxide including at least one of hafnium and zirconium (abstract of Ali). In regards to claim 17, Wu ‘335 as modified by Ali further discloses further comprising a support, wherein the first electrode layer is disposed between the support and the antiferroelectric layer in the thickness direction of the first electrode layer ([0039] of Wu ‘335). In regards to claim 19, Wu ‘335 as modified by Ali further discloses an electrical circuit comprising the capacitor according to claim 1 (see claim 1 rejection above) wherein the capacitor is mounted to the electrical circuit ([0052] of Wu ‘335). In regards to claim 20, Wu ‘335 as modified by Ali further discloses a circuit board comprising the capacitor according to claim 1 (see claim 1 rejection above), wherein the capacitor is mounted to an electrical circuit formed on the circuit board ([0052] & [0005] of Wu ‘335). In regards to claim 21, Wu ‘335 as modified by Ali further discloses an electronic device comprising the capacitor according to claim 1 (see claim 1 rejection above), wherein the capacitor is mounted to an electrical circuit on a circuit board, and the electronic device is equipped with the circuit board ([0052] & [0005] of Wu ‘335). In regards to claim 22, Wu ‘335 discloses an electricity storage device comprising: a battery ([0070] – it is noted cell phones have a battery); and a capacitor, the capacitor comprising: a first electrode layer (10 – fig. 1a; [0028]); a second electrode layer (20 – fig. 1a; [0028]); and a dielectric layer (15 – fig. 1a; [0028]) disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, wherein an inner portion of the first electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the first electrode layer when the first electrode layer is viewed in plan (fig. 1), an inner portion of the second electrode layer covers the dielectric layer, the inner portion surrounded by an outermost portion of the second electrode layer when the second electrode layer is viewed in plan (fig. 1), and the dielectric layer has a thickness differing from one point to another (fig. 1a). Wu ‘335 fails to disclose the dielectric is an antiferroelectric. Ali discloses an antiferroelectric dielectric for use in capacitors (abstract). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the dielectric of Ali as the dielectric of Wu ‘335 to obtain a capacitor wherein the dielectric has high energy storage capabilities. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In regards to claim 23, Wu ‘335 as modified by Ali further discloses wherein: an antiferroelectric layer comprises at least one selected from a group consisting of a first metal oxide, a second metal oxide, and a third metal oxide, the first metal oxide is expressed by HfO2, ZrO2, or Hfi-xZrxO2, where x satisfying 0<x<1, and has a fluorite structure, the second metal oxide is a metal oxide in which part of Hf in HfO2 or Hfi-xZrxO2 is substituted by Si or Al, where x satisfying 0<x<1, and the third metal oxide is a metal oxide in which part of Zr in ZrO2 or Hfi-xZrxO2 is substituted by Y, Ti, Sn, or Ce, where x satisfying 0<x<1 (conclusion of Ali). Claim(s) 1, 11, & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Laibowitz et al. (US 5,926,360) in view of Tan ‘913. In regards to claim 1, Laibowitz ‘360 discloses a capacitor comprising: a first electrode layer (42-43 – fig. 4; C6:L8-31); a second electrode layer (45-46 – fig. 4; C6:L8-31); and a dielectric layer (44 – fig. 4; C6:L8-31) disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, wherein an inner portion of the first electrode layer covers the antiferroelectric layer, the inner portion surrounded by an outermost portion of the first electrode layer when the first electrode layer is viewed in plan (fig. 4), an inner portion of the second electrode layer covers the antiferroelectric layer, the inner portion surrounded by an outermost portion of the second electrode layer when the second electrode layer is viewed in plan (fig. 4), and the dielectric layer has a thickness differing from one point to another (fig. 4). Laibowitz ‘360 fails to disclose the dielectric is an antiferroelectric. Tan ‘913 discloses an antiferroelectric dielectric (abstract). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the dielectric of Tan ‘913 as the dielectric of Wu ‘335 to obtain a capacitor wherein the dielectric has a high dielectric constant and high energy storage capabilities with ease of processing as well as with improved mechanical properties. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In regards to claim 11, Laibowitz ‘360 as modified by Tan ‘913 further discloses wherein the antiferroelectric layer includes a connecting portion between a pair of regions having different thicknesses, the connecting portion having a thickness varying continuously or stepwise from one of the pair of regions toward the other (fig. 4 of Laibowitz ‘360). In regards to claim 17, Laibowitz ‘360 as modified by Tan ‘913 further discloses further comprising a support (40), wherein the first electrode layer is disposed between the support and the antiferroelectric layer in the thickness direction of the first electrode layer (fig. 4 of Laibowitz ‘360). In regards to claim 18, Laibowitz ‘360 as modified by Tan ‘913 further discloses wherein the support has no empty space overlapping the antiferroelectric layer in plan view (fig. 4 of Laibowitz ‘360). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2010/0025817 – [0032] US 2020/0395435 – [0036] EP3557633A1 – teaches dielectric of capacitor can be ferroelectric or antiferroelectric THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David M Sinclair/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Show 1 earlier event
May 06, 2025
Non-Final Rejection mailed — §103
Aug 05, 2025
Response Filed
Nov 14, 2025
Non-Final Rejection mailed — §103
Jan 23, 2026
Interview Requested
Jan 29, 2026
Applicant Interview (Telephonic)
Jan 30, 2026
Examiner Interview Summary
Feb 12, 2026
Response Filed
May 22, 2026
Final Rejection mailed — §103 (current)

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