DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 6, 2026 has been entered.
Claims 1-30 are pending in this case. Claims 1, 4, 5, 17, 21, 24, 25, and 30 have been newly amended. No claims have been newly added or cancelled. This action is made Non-Final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10, 11, 15-24, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luu et al. (US 7,256,788) in view of Yang et al. (US 2011/0279463) and WOO et al. (US 2016/0329033).
As to claim 1, Luu et al. disclose an apparatus for display processing (Figure 2, computer system 200), comprising: a memory (e.g. main memory 202 (e.g. random access memory) and/or removable data storage device 204); and a processor (e.g. central processing unit (CPU) 201 with graphics processor (GPU) 211 of graphics subsystem 210) coupled to the memory (e.g. coupled to main memory 202 and/or removable data storage device 204 via chipset 203 and communication bus 290, column 5, lines 24-27) and, based on information stored in the memory (e.g. information and instructions, where column 5, lines 37-40 notes main memory 202 as well as removable data storage device 204 stores information and instructions for CPU 201), the processor (e.g. CPU 201 with GPU 211) is configured to: obtain a software-based indication (e.g. receive generated commands via an application thread) that indicates to start an execution of command packets (e.g. indicates to start execution, e.g. loading, of a first set of commands, e.g. graphics commands 331)(Figure 3A, column 7, lines 27-28 notes at the beginning of refresh cycle 301 (time 370), CPU sends graphics commands 331 to GPU, where step 410, column 6, lines 24-33 notes loading a first set of commands from a CPU into a GPU, where the first set of commands are loaded at the beginning of a graphics frame cycle, where column 6, lines 40-42 further notes an application thread of the CPU generated the first set of commands, thus considered the generated commands received by the CPU from the application thread the “software-based indication,” which then triggers loading of the received first set of commands from the CPU to the GPU, further considered the “start of execution” of the first set of commands); execute, based on the obtained software-based indication (e.g. based on the received first set of commands by application thread), a first set of command packets associated with a first region of interest (ROI) of a frame that is to be updated (e.g. GPU 211 executes the first set of commands (e.g. generated first set of commands by application thread) loaded by the CPU 201 associated with a first frame, e.g. frame A, to be updated, e.g. refreshed)(Figure 3A, column 7, lines 29-33 notes shortly after the graphics commands 331 are received, the GPU processes the commands and generates graphics data 351 which is forwarded to a frame buffer, the GPU processes the commands and forwards the resulting pixel data to the frame buffer before the refresh cycle 301 is complete); and execute, based on the obtained hardware-based indication (e.g. based on the interrupt signal), a second set of command packets associated with a second ROI of the frame that is to be updated (e.g. GPU 211 executes the second set of commands loaded by the CPU 201 associated with a second frame, e.g. frame B, to be updated, e.g. refreshed)(e.g. step 430, column 7, lines 1-22 notes when the GPU is ready to receive more commands, e.g. after executing the first set of commands and generating graphics data, the GPU forwards an interrupt signal, FLIP IRQ, to CPU which begins downloading more graphics commands to the GPU, Figure 3A, column 7, lines 45-54 further notes the time period beginning with the sending of the commands to the end of the GPU processing the commands is referred to as the rendering phase, where the time period from time 373 to 382 is the rendering phase for frame B, thus the process repeats for additional frames).
As noted above, Luu et al. disclose its GPU sending an interrupt signal, e.g. FLIP IRQ, to a CPU when it is ready to receive and process additional commands, which may be considered “obtain…a hardware-based indication.” However, Luu et al. differs from the invention defined in claim 1 in that Luu et al. do not disclose “…obtain, based on a transfer of pixel data from a buffer, a hardware-based indication that indicates that a second set of command packets associated with a second ROI of the frame is capable of execution…” Luu et al. also differ from the invention defined in claim 1 in that Luu et al. disclose each of the first and second command packets associated with respective frames, but do not disclose each of the first and second command packets associated with “a first region of interest (ROI)” of a frame and a “second ROI” of the frame, respectively.
Yang et al. disclose execute…a first set of command packets (e.g. execute drawing commands CD2 related to buffer 150, e.g. of Figure 1A, via drawing engine 120) associated with a first…frame that is to be updated (Figure 1B, step 1, [0023] notes processor 110 sends drawing commands CD2 related to buffer 150 to the drawing engine 120; step 2, [0023] notes once the drawing commands are received, drawing engine 120 draws graphics data for buffer 150); obtain, based on a transfer of pixel data from a buffer (e.g. based on the transfer of graphics data to a display, e.g. via display engine 130), a hardware-based indication (e.g. obtain, via drawing engine 120, a second notice signal NS2 from display engine 130) that indicates that a second set of command packets associated with a second…frame is capable of execution (e.g. that indicates buffer 150 flip is done, e.g. graphics data has been displayed and buffer is flushed, thus further capable of executing drawing commands CD1 related to buffer 140)(step 3, [0023] notes processor 110 sends an asynchronous flush command CFS2 related to buffer 150 to the drawing engine 120 to confirm that drawing commands CD2 are completed, step 4, [0023] further notes processor 110 sends the asynchronous flip command CFP2 related to buffer 150 to the display engine 130 in order to display the graphics data stored in buffer 150, step 7, [0024] notes drawing engine 120 flushes buffer 150, step 8, [0024] further notes drawing engine 120 then sends notice signal NS1 to notify buffer is capable of being flipped, step 10, [0024] notes a VSYNC interrupt and a first notice signal NS1 are received which indicates that buffer 150 is capable of being flipped, display engine 130 proceeds to flip buffer 150, step 11, [0024] further notes after buffer 150 is flipped, the display engine 130 sends a second notice signal NS2 to notify the drawing engine 120 that buffer 150 flip is done, e.g. now capable of executing drawing commands CD1 related to buffer 140, e.g. drawing graphics data related to buffer 140); and execute, based on the obtained hardware-based indication (e.g. execute, based on the second notice signal NS2 received from display engine 130 by drawing engine 120), the second set of command packets associated with the second…frame that is to be updated (e.g. drawing commands CD1 related to buffer 140)(step 12, [0024] further notes after receiving NS2 signal from display engine 130, the drawing engine 120 can now draw graphics data for buffer 140).
Luu et al. describes having multiple (e.g. double) frame buffers 215 and 217 as illustrated in Figure 2, which are utilized by the GPU for rendering and forwarding resulting pixel data. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Luu et al.’s double frame buffers and method of signaling when the GPU has completed executing commands and rendering pixel data with Yang et al.’s method of sending flush commands confirming whether drawing commands related to a buffer is completed and signals to notify when a buffer has been flipped to optimize use of the double buffers and send drawing commands immediately for execution, thus preventing delays in the system ([0023] of Yang et al.).
As described, Luu et al. modified with Yang et al. disclose commands associated with respective frames, but do not disclose commands associated with “a first region of interest (ROI)” of a frame and a “second ROI” of the frame, respectively.
WOO et al. disclose a first command packet associated with a first region of interest (ROI) and a second command packet associated with a second ROI of the frame (e.g. Figures 2 and 3 illustrate at least first partial region AR1 and second partial region AR2, where Figures 12B, 13B, 14B, and 15B illustrate protocols for setting command signal CMD_set according to the multiple partial update methods, e.g. Figures 12A, 13A, 14A, and 15A, respectively, where multiple partial updates are of different regions of interests (ROIs) of a frame, see associated text).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Luu et al. modified with Yang et al.’s system and method of full frame updates/refreshes, including executing commands associated with full frames, with WOO et al.’s method of performing multiple partial updates, e.g. executing commands associated with regions of interest of frames, to reduce processing time and requirements with updating full frames, thus updating only regions that have changed, and ultimately enhancing the performance of the system. It may be considered that the modification of Luu et al. and Yang et al. with WOO et al. may render the frames of Luu et al. and Yang et al. may encompass regions of interest as described in WOO et al.
As to claim 2, Luu et al. modified with Yang et al. and WOO et al. disclose the first ROI of the frame and the second ROI of the frame are associated with a partial frame update of the frame (further modified with WOO, Figures 2 and 3 illustrate at least first partial region AR1 and second partial region AR2, where Figures 12A, 13A, 14A, and 15A further describe multiple partial update methods, including the first ROI and the second ROI of the frame).
As to claim 3, Luu et al. modified with Yang et al. and WOO et al. disclose the first ROI of the frame is within a threshold distance of the second ROI of the frame (further modified with WOO, Figures 2 and 3 illustrate at least first partial region AR1 and second partial region AR2, where [0128] notes each of the first partial region AR1 and second partial region AR2 are separate regions, located on two sides of the display panel and have the same vertical size, but may be modified to have other positions, sizes, and shapes).
As to claim 4, Luu et al. modified with Yang et al. and WOO et al. disclose the pixel data is associated with the first ROI (Luu, modified with Yang, further modified with WOO, pixel data associated with first ROI), and wherein, to obtain the hardware-based indication (modified with Yang, obtain NS2 signal via drawing engine 120), the processor is configured to obtain the hardware-based indication based on a removal of the pixel data from the buffer (modified with Yang, as noted in claim 1, drawing engine 120 flushes buffer 150 and sends NS1 signal to notify display engine 130 that buffer 150 is capable of being flipped, then once a VSYNC interrupt and the first notice signal NS1 are received, display engine 130 proceeds to flip buffer 150 and sends a second notice signal NS2 to notify the drawing engine 120 that buffer 150 flip is done, thus notice signal NS2 is received based on graphics data being removed from buffer 150).
As to claim 10, Luu et al. modified with Yang et al. and WOO et al. disclose a command packet in the second set of command packets indicates that the second ROI is a last ROI for the frame (Luu, modified with Yang, further modified with WOO, e.g. second set of commands indicate a last ROI for the frame), wherein the processor is further configured to: execute, based on a second obtained software-based indication (Luu, e.g. based on (e.g. receiving second generated commands via the application thread), a third set of command packets associated with an ROI of a second frame that is to be updated (Luu, modified with Yang, further modified with WOO, e.g. execute a third set of commands associated with a ROI of a second frame)(Luu, modified with Yang, further modified with WOO, e.g. the process as noted in claim 1 may be repeated for a next, subsequent frame).
As to claim 11, Luu et al. modified with Yang et al. and WOO et al. disclose the hardware-based indication comprises an interrupt request (irq)(Luu, as noted in claim 1, interrupt signal, FLIP IRQ; modified with Yang, second notice signal NS2 indicating flip is done).
As to claim 15, Luu et al. modified with Yang et al. and WOO et al. disclose to execute the first set of command packets, the processor is configured to execute the first set of command packets via a configuration accelerator (Luu, e.g. as noted in claim 1, the first set of commands executed by GPU 211, considered a “configuration accelerator” as it is well known GPUs are hardware accelerators, e.g. for accelerating processing on behalf of a processor, e.g. CPU 201; modified with Yang, e.g. as noted in claim 1, executing drawing commands related to buffers via drawing engine 120, where [0021] notes drawing engine 120 part of a graphics processing apparatus 100), and wherein to execute the second set of command packets, the processor is configured to execute the second set of command packets via the configuration accelerator (Luu, e.g. as noted in claim 1, the second set of commands executed by GPU 211, considered a “configuration accelerator” as noted above; modified with Yang, e.g. as noted in claim 1, executing drawing commands related to buffers via drawing engine 120, where [0021] notes drawing engine 120 part of a graphics processing apparatus 100).
As to claim 16, Luu et al. modified with Yang et al. and WOO et al. disclose the obtained software-based indication is associated with a first latency (Luu, e.g. the generated first set of commands received by the CPU associated with a first latency, which may further include sending the first commands by the CPU to the GPU, the GPU processing the commands, and forwarding the results to a frame buffer, e.g. before 370 until 371), wherein the obtained hardware-based indication is associated with a second latency (Luu, e.g. receiving the interrupt signal, FLIP IRQ, associated with a second latency, where Figure 3A and associated text describes the interrupt signal received after processing of the first set of commands and forwarding to a frame buffer, e.g. between 371 and 372), and wherein the first latency is greater than the second latency (Luu, Figure 3A illustrates time associated with the first latency greater than the time associated with the second latency as described above).
As to claim 17, Luu et al. modified with Yang et al. and WOO et al. disclose wherein the pixel data is first pixel data, and wherein the processor is further configured to: obtain, based on an additional transfer of second pixel data from the buffer, a second hardware-based indication that indicates that a third set of command packets associated with a third ROI of the frame is capable of being executed (modified with Yang, where the process of Figure 1B may repeat for additional commands after step 12, thus a second NS2 signal may be received by the drawing engine 120 that buffer 140 flip is done, e.g. now capable of executing next drawing commands related to another buffer, e.g. drawing graphics data related to buffer 150); and execute, based on the obtained second hardware-based indication, the third set of command packets associated with the third ROI of the frame that is to be updated (modified with Yang, step 12, [0024] further notes after receiving NS2 signal from display engine 130, the drawing engine 120 can now draw graphics data for another buffer, e.g. buffer 150, e.g. execute next drawing commands)(modified with Yang, see also Figures 3A, 3B, 4A, and 4B where additional drawing commands may be executed using additional buffers).
As to claim 18, Luu et al. modified with Yang et al. and WOO et al. disclose the processor is further configured to: output an indication of at least one of the executed first set of command packets or the executed second set of command packets (Luu, e.g. as noted in claim 1, GPU processes the graphics commands and forwards the resulting pixel data to a frame buffer, which is further output to a display, where the resulting pixel data may be considered “an indication” of the executed first and second sets of commands; modified with Yang, as noted in claim 1, processor 110 may send an asynchronous flush command CFS2 related to buffer 150 to the drawing engine 120 to confirm that drawing commands CD2 are completed and send a asynchronous flip command CFP2 related to buffer 150 to the display engine 130 in order to display the graphics data stored in buffer 150, then drawing engine 120 may flush buffer 150 and send notice signal NS1 to notify buffer is capable of being flipped, e.g. indicating drawing commands CD2 have been executed or complete).
As to claim 19, Luu et al. modified with Yang et al. and WOO et al. disclose to output the indication of at least one of the executed first set of command packets or the executed second set of command packets (Luu, e.g. to output the resulting pixel data of the executed set of commands; modified with Yang, output NS1 signal), the processor is configured to: transmit the indication of at least one of the executed first set of command packets or the executed second set of command packets (Luu, transmit the resulting pixel data of the executed set of commands; modified with Yang, as noted in claim 18, NS1 signal is transmitted from drawing engine 120 to display engine 130); or store the indication of at least one of the executed first set of command packets or the executed second set of command packets (Luu, e.g. as noted in claims 1 and 18, GPU processes the graphics commands and forwards (e.g. transmits) the resulting pixel data to a frame buffer (e.g. to be stored therein)).
As to claim 20, Luu et al. modified with Yang et al. WOO et al. disclose the apparatus (Luu, Figure 2, computer system 200; modified with WOO, host processor 100a) is a wireless communication device comprising at least one of a transceiver or an antenna (Luu, e.g. signal communication port 208; modified with WOO, transmission (TX) interface 160) coupled to the processor (Luu, coupled to CPU 201 and/or GPU 211; modified with WOO, coupled to host processor 100a)(Luu, column 5, lines 43-45 notes signal communication port 208 provides a communication interface to exterior devices (e.g. an interface with a network); modified with WOO, [0139] notes transmission interface 160 as a high speed serial interface for communications).
Claims 21-24 are similar in scope to claims 1-4, respectively, and are therefore rejected under similar rationale.
As to claim 30, Luu et al. modified with Yang et al. and WOO et al. disclose a non-transitory computer-readable medium (Luu, Figure 2, main memory 202) storing computer executable code, the computer executable code (Luu, information and instructions), when executed by a processor (Luu, CPU 201 and/or GPU 211) (Luu, e.g. information and instructions, where column 5, lines 37-40 notes main memory 202 as well as removable data storage device 204 stores information and instructions for CPU 201), causes the processor to perform the steps as performed by the processor of claim 1. Please see the rejection and rationale of claim 1 above.
Claim(s) 6-9 and 26-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luu et al. (US 7,256,788) in view of Yang et al. (US 2011/0279463) and WOO et al. (US 2016/0329033) as applied to claims 1 and 21 above, and further in view of McCrary et al. (US 2011/0050713).
As to claim 6, Luu et al. modified with Yang et al. and WOO et al. do not disclose, but, McCrary et al. disclose the processor is further configured to (Figure 3, process 300, Figure 4, process 400, and Figure 6, process 409): configure, prior to the execution of the first set of command packets (e.g. prior to execution of commands by GPU 104), the first set of command packets (e.g. configure a first set of ring buffers 110 and indirect ring buffers 111) and a first set of command descriptors for the first set of command packets (e.g. configure, e.g. initialize, a first set of ring buffer configuration information stored in ring buffer work registers 112)(step 301, [0036] notes CPU 101 initializes a set of ring buffers in system memory 103 (e.g. as illustrated in Figures 1 and 2) for purposes of transferring command buffers to GPU 104, the initialization step may take place either at system startup or application startup, [0037] notes initialization includes memory allocation, the initialization of data structures corresponding to the ring buffers, and updating one or more registers used to communicate ring buffer configuration information to GPU 104, e.g. the number of ring buffers, the size of ring buffers, the size of indirect buffer area, and the like, [0038] further notes each ring buffer 110 is implemented as a circular array, with each element of the circular array intended to accommodate a pointer to a location in the indirect buffer area 111, the indirect buffer area 111 intended to accommodate a plurality of data structures corresponding to command buffers, e.g. each command buffer can include one or more commands to be executed by GPU and associated data, ring buffer work registers 112 utilized to convey information related to the ring buffer usage by CPU 101 to GPU 104, e.g. information such as the list of currently active ring buffers, a priority ordering of the active ring buffers as determined by CPU 101, allocation of active ring buffers to one or more GPU elements, can all be conveyed to GPU 104 by CPU 101 as well as information such as the current read and write pointers for each ring buffer, step 303, [0039] notes CPU 101 notifies GPU 104 of the ring buffer configuration, and step 305, [0040] notes writing commands to ring buffers, [0041]); configure, prior to the execution of the second set of command packets (e.g. prior to execution of commands by GPU 104), the second set of command packets (e.g. configure a second set of ring buffers 110 and indirect ring buffers 111) and a second set of command descriptors for the second set of command packets (e.g. configure, e.g. initialize, a second set of ring buffer configuration information stored in ring buffer work registers 112)(steps 301-303 repeated for second set of ring buffers 110, indirect buffers 111, and ring buffer work registers 112); and store, in a queue (e.g. ring buffer work registers 112), the first set of command descriptors and the second set of command descriptors (e.g. configuration information)(e.g. stored as noted above), wherein to execute the first set of command packets (e.g. to execute ring buffers 110 and indirect ring buffers 111), the processor (e.g. GPU 104) is configured to execute the first set of command packets based on the first set of command descriptors (e.g. execute the first set of ring buffer 110 based on configuration information stored in ring buffer work registers 112), and wherein to execute the second set of command packets (e.g. to execute ring buffers 110 and indirect ring buffers 111), the processor (e.g. GPU 104) is configured to execute the second set of command packets based on the second set of command descriptors (e.g. execute the second set of ring buffer 110 based on configuration information stored in ring buffer work registers 112)(Figure 4, step 401, [0044] and [0045] notes GPU 104 determines the configuration of ring buffers in system memory 103 through which it received command buffers from CPU 101, including monitoring the availability of ring buffers for processing and associated ring buffer work registers, step 405, [0046] and [0047] notes GPU 104 selects a subset of ring buffers 110 for processing and execution, step 407, [0048] notes GPU 104 selects command buffers for execution on the GPU 104 according to priority criteria (e.g. obtained from ring buffer work registers 112 as noted above), step 409, [0049] notes selected commands are executed by GPU 104 according to priority orderings (e.g. obtained from ring buffer work registers 112 as noted above), where Figure 6 describes executing a second ring buffer by GPU 104).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Luu et al. modified with Yang et al. and WOO et al.’s system and method of executing command packets associated with frames with McCrary et al.’s method of configuring command packets and command descriptors prior to execution to effectively allocate the command packets and command descriptors as they are ready and available for execution by the executing processor once needed (see Background of McCrary et al.).
As to claim 7, Luu et al. modified with Yang et al., WOO et al., and McCrary et al. disclose the processor is further configured to: retrieve, from the memory (further modified with McCrary, e.g. from system memory), the first set of command packets (further modified with McCrary, e.g. the first set of ring buffers 110 and indirect ring buffers 111) based on the stored first set of command descriptors (further modified with McCrary, e.g. based on configuration information stored in ring buffer work registers 112); and retrieve, from the memory (further modified with McCrary, e.g. from system memory), the second set of command packets (further modified with McCrary, e.g. the first set of ring buffers 110 and indirect ring buffers 111) based on the stored second set of command descriptors (further modified with McCrary, e.g. based on configuration information stored in ring buffer work registers 112)(further modified with McCrary, e.g. as noted in claim 6 above, step 401 notes determining ring buffer configuration, which is obtained from ring buffer work registers 112, which stores information such as the list of currently active ring buffers, a priority ordering of the active ring buffers as determined by CPU 101, allocation of active ring buffers to one or more GPU elements, can all be conveyed to GPU 104 by CPU 101 as well as information such as the current read and write pointers for each ring buffer, then further in step 405, GPU selects a subset of ring buffers 110 for processing and execution, where [0047] notes the subset of ring buffers for execution can be brought into GPU local memory or GPR (e.g. retrieved from system memory) in preparation for processing within GPU 104).
As to claim 8, Luu et al. modified with Yang et al., WOO et al., and McCrary et al. disclose to retrieve the first set of command packets from the memory (further modified with McCrary, e.g. retrieve first set of ring buffers from system memory 102), the processor (further modified with McCrary, e.g. GPU 104) is configured to retrieve the first set of command packets from the memory via an advanced eXtensible interface (AX) (further modified with McCrary, e.g. retrieve the first set of ring buffers from system memory 102 via communication infrastructure 105)(further modified with McCrary, step 405, GPU selects a subset of ring buffers 110 for processing and execution, where [0047] notes the subset of ring buffers for execution can be brought into GPU local memory or GPR (e.g. retrieved from system memory) in preparation for processing within GPU 104 via communication infrastructure 105, where [0033] notes communication infrastructure 105 can include one or more communication buses such as Peripheral Component Interconnect (PCI), Advanced Graphics Port (AGP), and the like, where AXIs are well known in the art similarly to the communication buses described, which would render similar results as described), and wherein to retrieve the second set of command packets from the memory (further modified with McCrary, e.g. retrieve second set of ring buffers from system memory 102), the processor (further modified with McCrary, e.g. GPU 104) is configured to retrieve the second set of command packets from the memory via the AXI (further modified with McCrary, e.g. retrieve the first set of ring buffers from system memory 102 via communication infrastructure 105)(further modified with McCrary, step 405 repeated for second set of ring buffers via communication infrastructure 105 as noted above).
As to claim 9, Luu et al. modified with Yang et al., WOO et al., and McCrary et al. disclose the stored first set of command descriptors comprises a first set of memory addresses and sizes of the first set of command packets (further modified with McCrary, e.g. first set of ring buffer work registers comprises memory addresses (locations) and sizes of ring buffers) and the stored second set of command descriptors comprises a second set of memory addresses and sizes of the second set of command packets (further modified with McCrary, e.g. second set of ring buffer work registers comprises memory addresses (locations) and sizes of ring buffers)(further modified with McCrary, e.g. as noted in claim 6 above, [0037] and [0038] notes ring buffer work registers 112, which stores information such as the number of ring buffers, the size of ring buffers, the size of indirect buffer area, and the like (e.g. memory sizes) as well as information such as the list of currently active ring buffers, a priority ordering of the active ring buffers as determined by CPU 101, allocation of active ring buffers to one or more GPU elements, can all be conveyed to GPU 104 by CPU 101, and information such as the current read and write pointers for each ring buffer (e.g. memory locations, known as addresses)), wherein to retrieve the first set of command packets based on the stored first set of command descriptors, the processor is configured to retrieve the first set of command packets based on the first set of memory addresses and sizes (further modified with McCrary, e.g. retrieve first set of ring buffers based on information, e.g. memory addresses and sizes, stored in first set of ring buffer work registers), and wherein to retrieve the second set of command packets based on the stored second set of command descriptors, the processor is configured to retrieve the second set of command packets based on the second set of memory addresses and sizes (further modified with McCrary, e.g. retrieve second set of ring buffers based on information, e.g. memory addresses and sizes, stored in second set of ring buffer work registers)(further modified with McCrary, e.g. as noted in claim 6 above, step 401 notes determining ring buffer configuration, which is obtained from ring buffer work registers 112, which stores information as noted above, then further in step 405, GPU selects a subset of ring buffers 110 for processing and execution, where [0047] notes the subset of ring buffers for execution can be brought into GPU local memory or GPR (e.g. retrieved from system memory) in preparation for processing within GPU 104).
Claims 26-29 are similar in scope to claims 6-9, respectively, and are therefore rejected under similar rationale.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luu et al. (US 7,256,788) in view of Yang et al. (US 2011/0279463) and WOO et al. (US 2016/0329033) as applied to claim 1 above, and further in view of Banker et al. (US 5,579,057).
As to claim 12, Luu et al. modified with Yang et al. and WOO et al. disclose to execute the first set of command packet…for the first ROI… and to execute the second set of command packets…for the second ROI (Luu, modified with Yang, further modified with WOO, see claim 1), but do not disclose, but Banker et al. disclose the processor is configured to configure a first set of configuration registers for the first ROI, and the processor is configured to configure a second set of configuration registers for the second ROI (Figure 14 illustrates mapping of configuration registers R1-R12, which comprise various types of parameters and attributes, where column 13, lines 7-19 notes digital processor 302 is controlled by the control processor 128 by reading and writing the registers R1-R12 shown in Figure 14, the display attributes for the on-screen display can be controlled by loading and reading particular registers in the digital processor 302, e.g. the type of screens which can be displayed and their location on the display area of the television receiver are provided by border screen parameters register R2, a symbol screen parameters register R4, and a graphics screen parameters register R5).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Luu et al. modified with Yang et al. and Woo et al.’s system and method of executing command packets associated with ROIs of frames with Banker et al.’s method of configuring configuration registers for each ROI of frames to control the executing processor to appropriately render the ROIs for display (see Figure 14 and associated text of Banker et al.).
As to claim 13, Luu et al. modified with Yang et al., WOO et al., and Banker et al. disclose the first set of command packets comprises a first operation code (OPCODE) and the second set of command packets comprises a second OPCODE (further modified with Banker, e.g. commands includes a first OpCode and a second OpCode), wherein the processor is further configured to: decode the first OPCODE, wherein to configure the first set of configuration registers, the processor is configured to configure the first set of configuration registers based on the decoded first OPCODE (further modified with Banker, e.g. decode the first opcode and further configure a first set of configuration registers based on the decoded first OpCode); and decode the second OPCODE, wherein to configure the second set of configuration registers, the processor is configured to configure the second set of configuration registers based on the decoded second OPCODE (further modified with Banker, e.g. decode a second OpCode and further configure a second set of configuration registers based on the decoded second OpCode)(further modified with Banker, e.g. column 15, lines 61 thru column 16, lines 7 notes control interface circuit 306 provides a means for the control processor 128 to access the configuration registers R1-R12 (considered to encompasses first set and second set of configuration registers) of the digital processor 302, where circuit 306 decodes the operational commands, OpCode (e.g. decode first and second OpCode) and addresses ADD of the control microprocessor 128 to determine which configuration register is to be read or written, and with what data, to provide the configuration data, to provide the configuration data and to read the status of the digital processor 302, the control interface circuit 306 has an 8 bit data bus DataIN coupled to all of the configuration registers for the write operation, and an 8 bit data bus DataOut coupled to the output of all of the configuration registers R1-R12 for the read operation, the outputs of the configuration registers R1-R12 are then used to provide control signals and configuration data to the other circuits (e.g. configure first and second set of configuration registers)).
As to claim 14, Luu et al. modified with Yang et al., WOO et al., and Banker et al. disclose the first OPCODE comprises a first non-operation, a first register write operation, a first register modify operation, a first single block write operation, a first incremented block write operation, a first multiple block write operation, a first look-up table (LUT) operation, or a first reserved operation, and wherein the second OPCODE comprises a second non-operation, a second register write operation, a second register modify operation, a second single block write operation, a second incremented block write operation, a second multiple block write operation, a second look-up table (LUT) operation, or a second reserved operation (further modified with Banker, as noted in claim 13, OpCode comprises at least read operations and write operations for respective configuration registers, e.g. first and second set of registers).
Allowable Subject Matter
Claims 5 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Dependent claims 5 and 25 similarly recite, “…wherein the pixel data is associated with the first ROI, and wherein, to obtain the hardware-based indication, the processor is configured to obtain the hardware-based indication before the pixel data has been fully transferred based on a counter associated with the transfer of the pixel data that has reached a software programmable value…” The prior art of record fails to teach or suggest, singly or combined, the limitations of claims 5 and 25 as recited.
Response to Arguments
Applicant's arguments filed January 6, 2026 have been fully considered but they are not persuasive. Applicant amends independent claims 1, 21, and 30 to similarly recite, “…“…obtain, based on a transfer of pixel data from a buffer, a hardware-based indication that indicates that a second set of command packets associated with a second ROI of the frame is capable of execution…” Applicant argues on pages 11-15 of the Amendment filed that the prior art of record, e.g. Luu in view of WOO, fails to teach or suggest the limitations of the claims as now amended. However, in light of the amendments of independent claims 1, 21, and 30, the claims are now rejected in view of newly found reference, Yang et al. (US 2011/0279463). Please see the rejection and notes regarding the claims above.
Applicant’s arguments, see page 15, filed January 6, 2026, with respect to claims 5 and 25 have been fully considered and are persuasive. Dependent claims 5 and 25 have been amended to similarly recite, “…wherein the pixel data is associated with the first ROI, and wherein, to obtain the hardware-based indication, the processor is configured to obtain the hardware-based indication before the pixel data has been fully transferred based on a counter associated with the transfer of the pixel data that has reached a software programmable value…” The prior art of record fails to teach or suggest, singly or combined, the limitations of claims 5 and 25. Therefore, the 35 U.S.C. 103 claim rejection of claims 5 and 25 has been withdrawn.
Conclusion
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617