Prosecution Insights
Last updated: May 29, 2026
Application No. 18/485,470

DISPLAY PANEL AND DISPLAY DEVICE

Non-Final OA §102§103
Filed
Oct 12, 2023
Priority
May 12, 2022 — CN 202210518090.8 +1 more
Examiner
SUTEERAWONGSA, JARURAT
Art Unit
2623
Tech Center
2600 — Communications
Assignee
Yungu (Gu’An) Technology Co. Ltd.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
288 granted / 432 resolved
+4.7% vs TC avg
Strong +33% interview lift
Without
With
+33.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
14 currently pending
Career history
453
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
94.8%
+54.8% vs TC avg
§102
0.9%
-39.1% vs TC avg
§112
2.7%
-37.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 432 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 4, 7, 12-14, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0158054 A1 to Cha. As to claim 1, Cha discloses a display panel (DD, DP) having a display area (DA) and a bezel area (NDA) (Figs. 3, 9, Pars. 81, 87), wherein the bezel area (NDA) comprises a first bezel area (FTA, PDA) and a second bezel area (top region of SUB) that are located on opposite sides of the display area (DA) (Figs. 3, 9, Par. 101), and the display panel (DD, DP) comprises: a cathode (EL2) disposed in the display area (DA) and the bezel area (FTA) (Figs. 3, 9, Pars. 123, 131); a power supply connection portion (CL2) comprising a first connection portion (CL2 in FTA region) and a second connection portion (CL2 in top region of SUB) (Figs. 3, 9, Par. 120), wherein the first connection portion (CL2 in FTA region) is connected to the cathode (EL2) in the first bezel area (FTA) (Figs. 3, 9, Par. 120, see also Pars. 123, 131), the second connection portion (CL2 in top region of SUB) is connected to the cathode (EL2) in the second bezel area (top region of SUB) (Figs. 3, 9, Par. 120, see also Pars. 123, 131), and the first connection portion (CL2 in FTA region) and the second connection portion (CL2 in top region of SUB) are configured to supply power to the cathode (EL2) (Figs. 3, 9, Par. 120, see also Pars. 123, 131); and at least one bonding connection portion (P1, PP2) located in the first bezel area (FTA, PDA) (Figs. 3, 9, Par. 123, see also Pars. 120, 131) and connecting the first connection portion (CL2 in FTA region) and the second connection portion (CL2 in top region of SUB) (Figs. 3, 9, Par. 120, see also Pars. 123, 131). As to claim 2, Cha discloses the power supply connection portion (CL2) further comprises a left connection portion (CL2 in the left NDA region) and a right connection portion (CL2 in the right NDA region) that are located in the bezel area (NDA) (Figs. 3, 9, Pars. 116, 123), the left connection portion (CL2 in the left NDA region) is connected between a first end of the first connection portion (left end of CL2 in FTA region) and a first end of the second connection portion (left end of CL2 in top region of SUB) (Figs. 3, 9, Pars. 116, 120, see also Pars. 123, 131), and the right connection portion (CL2 in the right NDA region) is connected between a second end of the first connection portion (right end of CL2 in FTA region) and a second end of the second connection portion (right end of CL2 in top region of SUB) (Figs. 3, 9, Pars. 116, 120, see also Pars. 123, 131). As to claim 4, Cha discloses the display panel (DD, DP) further comprises a first conductive line (LP) (Figs. 3, 9, Pars. 100, 102) and a second conductive line (EL3) (Figs. 3, 9, Par. 109), wherein the first conductive line (LP, PL2) is connected between the first connection portion (CL2 in FTA region) and a corresponding bonding connection portion (P1) (Figs. 3, 9, Pars. 100, 102); and the second conductive line (EL3) is connected between the second connection portion (CL2 in top region of SUB) and a corresponding bonding connection portion (PP2) (Figs. 3, 9, Pars. 108-109). As to claim 7, Cha discloses the first conductive line (LP) and the second conductive line (EL3 in top region of SUB) are located in the bezel area (DA) (Figs. 3, 9, Pars. 100, 102, 108), two second conductive lines (CL2 in left NDA region and right NDA region) are provided (Figs. 3, 9, Par. 116), one of the two second conductive lines (CL2 in left NDA region) is connected between a first end of the second connection portion (left end of CL2 in top region of SUB) and a corresponding bonding connection portion (PP2_1) (Figs. 3, 9, Pars. 116, 120, see also Pars. 123, 131), and another one of the two second conductive lines (right end of CL2 in top region of SUB) is connected between a second end of the second connection portion (left end of CL2 in top region of SUB) and a corresponding bonding connection portion (PP2_2) (Figs. 3, 9, Pars. 116, 120, see also Pars. 123, 131). As to claim 12, Cha does not expressly disclose the display panel (DD, DP) comprises a substrate (SUB) and an anode layer (EL1) on the substrate (SUB) (Figs. 3, 6, 9, Pars. 131, 169), and the anode layer (EL1) comprises a plurality of anodes (Figs. 3, 6, 9, Pars. 131, 169); and a vertical projection of the second conductive line (EL3) on the substrate (SUB) does not overlap a vertical projection of an anode (EL1) of the plurality of anodes on the substrate (SUB) (Figs. 3, 6, 9, Pars. 131, 169 where EL1 and EL3 are arranged in vertically and do not overlap each other as shown in Fig.6 ). As to claim 13, Cha does not expressly disclose the display panel (DD, DP) comprises a substrate (SUB) and an anode layer (EL1) on the substrate (SUB) (Figs. 3, 6, 9, Pars. 131, 169), and the anode layer (EL1) comprises a plurality of anodes (Figs. 3, 6, 9, Pars. 131, 169); and a vertical projection of the second conductive line (EL3) on the substrate (SUB) overlaps a vertical projection of an anode (EL1) of the plurality of anodes on the substrate (SUB) (i.e. EL1 and EL3 are horizontally connected to CL1 and CL3, EL1 and EL3 arranged in horizontal are a part of CL1 and CL3 where they overlapp each other as shown in Fig.7a). As to claim 14, Cha discloses the at least one bonding connection portion (PP2) is configured to access a power supply voltage and connects the first connection portion (CL2 in FTA region) and the second connection portion (CL2 in top region of SUB) to supply power to the cathode in the first bezel area through the first connection portion (Figs. 3, 9, Par. 120, see also Pars. 123, 131) and to supply power to the cathode (EL2) in the second bezel area through the second connection portion (Figs. 3, 9, Par. 120, see also Pars. 123, 131). As to claim 19, Cha discloses the display device further comprises a flexible connection piece (FPCB) bonded to the bonding connection portion (Fig. 10, Pars. 274-275), at least one flexible connection piece (FPCB) is provided, and each of the at least one flexible connection piece (FPCB) is bonded to a corresponding bonding connection portion (Fig. 10, Pars. 274-275). As to claim 20, Cha discloses wherein lines disposed on a flexible connection piece of the at least one flexible connection piece (Fig. 10, Pars. 274-275) and connected to corresponding bonding connection portions are shorted (Fig. 10, Pars. 274-275). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0158054 A1 to Cha and US 2018/0247593 A1 to Ni et al. (Ni). As to claim 3, Cha discloses the first connection portion (CL2 in FTA region) extends along an edge of the cathode (lower edge of EL2) located in the first bezel area (FTA, PDA) and the second connection portion (CL2 in top region of SUB) extends along an edge of the cathode (top edge of EL2) located in the second bezel area (top region of SUB) (Figs. 3, 9, Pars. 116, 120, 123). Cha does not expressly disclose the first connection portion and the second connection portion are strip-shaped. Ni discloses the first connection portion (111) and the second connection portion (112) are strip-shaped (Figs. 1-2, Pars. 29, 31), the first connection portion (111) extends along an edge of the active area (101) located in the first bezel area (lower region of 100) (Figs. 1-2, Pars. 29, 31) and the second connection portion (112) extends along an edge of the active area (101) located in the second bezel area (top region of 100) (Figs. 1-2, Par. 29, 31). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Cha with the teaching of Ni to optimize the brightness homogeneity of the screen as suggested by Ni (Par. 32). As to claim 16, Cha discloses the first bezel area (FTA, PDA) is a lower bezel area (Figs. 3, 9, Par. 101), the second bezel area is an upper bezel area (top region of SUB) (Figs. 3, 9, Par. 101), the bezel area further comprises a left bezel area (left NDA region) and a right bezel area (right NDA region) (Figs. 3, 9, Pars. 116, 123), Cha does not expressly disclose the left connection portion and the right connection portion are strip-shaped, wherein the left connection portion is connected to the cathode in the left bezel area and extends along an edge of the cathode located in the left bezel area, and the right connection portion is connected to the cathode in the right bezel area and extends along an edge of the cathode located in the right bezel area. Ni discloses the left connection portion (113) and the right connection portion (114) are strip-shaped (Fig. 2, Pars. 29, 31), wherein the left connection portion is connected to the wirings Xn (e.g. cathode) in the left bezel area (Fig. 2, Par. 32) and extends along an edge of the wirings Xn located in the left bezel area (Fig. 2, Par. 32), and the right connection portion (114) is connected to the wirings Xn (e.g. cathode) in the right bezel area (Fig. 2, Par. 32) and extends along an edge of the wirings Xn located in the right bezel area (Fig. 2, Par. 32). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Cha with the teaching of Ni to optimize the brightness homogeneity of the screen as suggested by Ni (Par. 32). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0158054 A1 to Cha and US 2020/0357875 A1 to Wang. As to claim 18, Cha discloses the display panel (DD, DP) comprises a substrate (SUB) and an anode layer (EL1) and a light-emitting layer (LD1) that are disposed on the substrate (SUB) (Fig. 6, Par. 146). Cha does not expressly disclose the light-emitting layer is disposed between the anode layer and the cathode, and the power supply connection portion is disposed in a same layer as the anode layer. Wang discloses the light-emitting layer (72) is disposed between the anode layer (711, 712) and the cathode (73) (Fig. 2, Par. 37) and the power supply connection portion is disposed in a same layer as the anode layer (5) (Figs. 1-3, Par. 28). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Cha with the teaching of Wang to provide an improved display device as suggested by Wang (Par. 13). Allowable Subject Matter Claims 5-6, 8-11, 15, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The allowable subject is: a ratio of a resistance of the first conductive line to a resistance of the second conductive line is positively correlated with a ratio of a voltage value of a signal to which the first conductive line is connected and a voltage value of a signal to which the second conductive line is connected, with all the limitation of claim 5 and any intervening claims. The allowable subject is: a resistance of the first conductive line is equal to a resistance of the second conductive line, with all the limitation of claim 6 and any intervening claims. The allowable subject is: the second conductive line comprises a backbone conductive line and a plurality of branch conductive lines, the backbone conductive line is connected to a corresponding bonding connection portion, and a branch conductive line of the plurality of branch conductive lines is connected between the backbone conductive line and the second connection portion; and the backbone conductive line extends in a first direction, and the branch conductive line extends in a second direction and passes through the display area, wherein the first direction intersects the second direction. with all the limitation of claim 8 and any intervening claims. The allowable subject is: the pixel circuit comprises a plurality of metal layers, and the first conductive line and the second conductive line are disposed in a same layer as at least one of the plurality of metal layers, with all the limitation of claim 17 and any intervening claims. Inquiries Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARURAT SUTEERAWONGSA whose telephone number is (571)270-7361. The examiner can normally be reached Monday thru Thursday, 8:30AM to 4:00PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JARURAT SUTEERAWONGSA/Examiner, Art Unit 2623 /CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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Prosecution Timeline

Oct 12, 2023
Application Filed
Apr 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+33.4%)
3y 1m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 432 resolved cases by this examiner. Grant probability derived from career allowance rate.

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