DETAILED ACTION Notice to Applicant The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1-12 are pending. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. On lines 7-8 of claim 1, the Applicant recites “each of said signal transmitting circuit sets including at least two of said signal transmitting circuits” . However, it is unclear to the Examiner as to how “each of the transmitting circuit sets” includes “at least two transmitting circuits” for the case when N = 3 (i.e. How do each of the transmitting circuit sets include at least two transmitting circuits (to give a total of a minimum of four transmitting circuits) if a number (N) of signal transmitting circuits is capable of being N=3?), thereby rendering the claim to be vague and indefinite. The Examiner construes that at least one of the transmitting circuit sets includes at least two signal transmitting circuits. On line 14 of claim 1, the Applicant recites “at least two balanced digital signal ”. However, it is unclear to the Examiner as to how “at least two balanced digital signal ” are generated by “said signal transmitting circuits” for the case when N = 3 (i.e. How are there “at least two balanced digital signal” (to give a total of a minimum of four transmitting circuits) if a number (N) of signal transmitting circuits is capable of being N=3?), thereby rendering the claim to be vague and indefinite. The Examiner construes that at least one balanced digital signal is generated by said signal transmitting circ uits. Claims 2- 12 are rejected by virtue of their dependency to claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 and 9-12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kraz US Patent 10,263,591 . As per claims 1 and 9-12 , Kraz discloses in Fig. 6 an in-phase noise suppression device ( e.g. device 600 which comprises a common mode (i.e. “in-phase”) noise filter therein ) comprising: as per claim 1, a signal transmitting unit ( e.g. U, V, and W lines ) including a number (N) of signal transmitting circuits, where N ≥ 3 ( e.g. N = 3 ) , each of said signal transmitting circuits having an input terminal ( e.g. left ends thereof ) and an output terminal ( e.g. right ends thereof ) , receiving a level signal at said input terminal thereof ( Col. 5 lines 17-21 , digital signal from controller 20 of digital device 10 ) , and outputting the level signal at said output terminal thereof, said signal transmitting circuits cooperatively constituting at least two signal transmitting circuit sets ( e.g. first set comprising U and V lines and second set comprising W line ) , each (i.e. at least one) of said signal transmitting circuit sets including at least two of said signal transmitting circuits ( e.g. first set comprising U and V lines ) , and forming a signal transmitting channel for transmitting a balanced digital signal ( e.g. balanced differential digital signal on lines U, V, and W ) ; and a grounding unit ( e.g. ground line G ) including a grounding circuit ( e.g. ground ) that is connected to said signal transmitting unit; wherein the level signals respectively received by said signal transmitting circuits at said input terminals thereof, when being respectively transmitted along said signal transmitting circuits, generate at least two balanced digital signal s (i.e. at least one balanced digital signal) and in-phase noise ( Abstract; The digital signal being propagated from the left ends to the right ends create common mode noise and inductor 210 suppresses the noise from the balanced signal to ground. ) ; wherein said signal transmitting unit and said grounding circuit cooperatively constitute a noise suppressive device ( e.g. common mode inductor 210 and capacitors 260 ) so as to suppress the in-phase noise generated in said signal transmitting circuits ( Abstract; a choke in the ground wire suppress common mode (i.e. “in-phase”) noise. ) ; as per claim s 9 -1 1 , wherein each of said signal transmitting circuits includes: a first passive element group ( e.g. differential inductors 220 ) connected to said input terminal of said signal transmitting circuit and an internal node ( e.g. nodes between inductors 220 and 250 in each line U, V, and W ) of said signal transmitting circuit; a second passive element group ( e.g. inductors 250 ) connected to said internal node /input terminal of said signal transmitting circuit and said output terminal of said signal transmitting circuit ( The inductors 250 are connected to the nodes between inductors 220 and 250 and to the left and right ends of the circuit 600. ) ; and a third passive element group ( e.g. capacitors 260 ) connected to said internal node of said signal transmitting circuit and said grounding circuit ( The capacitors 260 are electrically connected to the ground and are electrically connected to the nodes between the inductors 220 and 250. ) ; each of said first to third passive element groups including at least one of an inductive element, a capacitive element, or a resistive element ( e.g. capacitors 260 ) ; and as per claim 12, wherein said grounding circuit includes at least one of an inductive element , a capacitive element, or a resistive element ( e.g. inductor choke 210 ) . Allowable Subject Matter Claim s 2-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT RAKESH PATEL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-0961 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9AM-5PM EST M-F . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAKESH B PATEL/ Primary Examiner, Art Unit 2843