Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-9 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Blais (US 2003/0173498).
Regarding claims 1, 8, Blais teaches a method of sensing in a quantum system (para. 0091) comprising supplying a bias current through a JJ, the bias current less than a first value of a critical current of the JJ (para. 0091), measuring an output voltage of the JJ (voltmeter; para. 0093), wherein responsive to a change in one or more charge islands coupled to the JJ, the critical current is reduced to a second value less than the bias current , causing a voltage drop across the JJ (para. 0091).
Regarding claim 2, 9, Blais teaches that the superconducting island is a charge qubit (includes 2 dots; para. 0035).
Regarding claim 5, Blais teaches that the readout for the state of the mesoscopic charge device (island) and updating the critical current of the JJ to a second value responsive to the change in charge of the one or more charge islands (para. 0089-0091).
Regarding claim 6, 8; Blais teaches the JJ is included in a single electron transistor (meets limitation of a JJFET; para. 0051) wherein the one or more charge islands are capacitively coupled to a gate of the JJFET (single electron transistor meets this structural limitation ; para. 051), wherein the bias current is supplied by a current source coupled to a source or drain of the JJFET (single electron transistor meets this structural limitation ; para. 051).
Regarding claim 7, Blais teaches that the JJ is included in a pair of series connected JJs (single electron transistor meets this structural limitation ; para. 051), wherein the charge island are capacitively coupled between the junctions of the pair (fig. 4, #120-4 is provided between the jjs 120-1 and 120-2), wherein the bias current is supplied by a current source coupled with one of the JJs of the pair (para. 0075).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3,10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blais.
Regarding claim 3, 10, it would have been obvious to provide multiple charge islands as it would have been obvious to provide for duplication of parts. See MPEP 2144.04 (VI) (B).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blais (US 2003/0173498) in view of Pan (US 2013/0082617).
Blais teaches a product as described above in claim 8, but fails to teach the shunt resistor coupled between the source and the drain of the JJFET.
Pan, however, teaches a circuit (abstract) wherein the shunt resistor is connected between the drain and the source of the transistor for the purpose of providing parallel connection (para. 0036).
Therefore, it would have been obvious to one of ordinary skill in the art to provide the shunt resistor connected between the drain and the source of the transistor in Blais in order to provide parallel connection as taught by Pan.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blais in view of Zorin (“Quantum-limited electrometer based on single cooper pair tunneling.”).
Blais teaches a product as described above in claim 8, but fails to teach measurement circuitry coupled to the other of the source or the drain of the JJFET.
Zorin, however, teaches a SCPT (abstract) wherein it is known to provide an amplifier coupled to the output (drain) for the purpose of providing reliable pickup of the output signal (page 4, left column).
Therefore, it would have been obvious to one of ordinary skill in the art to provide an amplifier coupled to the output (drain) in Blais in order to provide reliable pickup of the output signal as taught by Zorin.
Allowable Subject Matter
Claim 4, 11, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to teach or suggest some or all of the capacitors have different capacitance values in combination with 4, 3, and 1 and alternatively 11, 10, 8.
The prior art of record fails to teach one or more charge islands capacitively coupled to a node between the JJs of the pair in combination with the limitations of claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A WARTALOWICZ whose telephone number is (571)272-5957. The examiner can normally be reached Monday-Friday 9 am - 5 pm.
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/PAUL A WARTALOWICZ/ Primary Examiner, Art Unit 1735
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