DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the application filed October 13, 2023.
Specification
The abstract of the disclosure is objected to because “comprises” should have been includes in lines 1 and 2. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin (US 2008/0283937 A1).
In regard to claim 1, Shin teaches a semiconductor device comprising: a gate cut portion 65/80 disposed between a first gate region 40 (left side) and a second gate region 40 (right side); wherein the gate cut portion 65/80 comprises a dielectric liner layer 65 disposed around a vacant area 80; wherein the dielectric liner layer 65 encloses the vacant area 80; and wherein the gate cut portion 65/80 isolates the first gate region 40 from the second gate region 40 (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 2, Shin teaches the vacant area 80 comprising air (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 3, Shin teaches the first gate region 40 (left side) and the second gate region 40 (right side) contacting the dielectric liner layer 65 of the gate cut portion 65/80 (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 4, Shin teaches the gate cut portion 65/80 being further disposed between a first source/drain region 15 (left side) and a second source/drain region 15 (right side) (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 5, Shin teaches a source/drain contact 75 disposed on one of the first source/drain region 15 (left side) and the second source/drain region 15 (right side), wherein part of the gate cut portion 65/80 contacts the source/drain contact 75 (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 8, Shin teaches part of the gate cut portion 65/80 disposed in an isolation region (region between 40 (left & right)) (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 18, Shin teaches a semiconductor device comprising: a first transistor comprising a first gate region 40 (left side); a second transistor comprising a second gate region 40 (right side); and an isolation structure 65/80 disposed between and contacting the first gate region 40 (left side) and the second gate region 40 (right side), wherein the isolation structure 65/80 comprises a dielectric liner layer 65 disposed around a vacant area 80, and wherein the dielectric liner layer 65 encloses the vacant area 80 (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 19, Shin teaches the vacant area 80 comprising air (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
In regard to claim 20, Shin teaches the first transistor further comprising a first source/drain region 15 (left side); the second transistor further comprises a second source/drain region 15 (right side); and the isolation structure 65/80 is further disposed between the first source/drain region 15 (left side) and the second source/drain region 15 (right side) (Figure 12, pages 1-2, paragraphs [0014]-[0054]).
Claim(s) 12-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando et al. (US 2019/0157414 A1).
In regard to claim 12, Ando et al. teach a semiconductor device comprising: a first nanosheet structure 202 comprising: a first gate region 904 (left side) including a first plurality of gate structures; and a first plurality of channel layers 106 (left side) alternately stacked with the first plurality of gate structures 904 (left side); a second nanosheet structure 204 comprising: a second gate region 904 (right side) including a second plurality of gate structures 904; and a second plurality of channel layers 106 (right side) alternately stacked with the second plurality of gate structures 904 (right side); and a gate cut portion 1202 disposed between the first gate region 904 (left side) and the second gate region 904 (right side); wherein the gate cut portion 1202 comprises a dielectric liner layer (dark element of 1202) disposed around a vacant area (oval element of 1202); wherein the dielectric liner layer (dark element of 1202) encloses the vacant area (oval element of 1202); and wherein the gate cut portion 1202 isolates the first gate region 904 (left side) from the second gate region 904 (right side) (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
In regard to claim 13, Ando et al. teach the vacant area (oval element of 1202) comprising air (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
In regard to claim 14, Ando et al. teach the first gate region 904 (left side) and the second gate region 904 (right side) contact the dielectric liner layer (dark element of 1202) of the gate cut portion 1202 (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
In regard to claim 15, Ando et al. teach a first source/drain region 802 (left side) disposed on a side of the first nanosheet structure 202; and a second source/drain region 802 (right side) disposed on a side of the second nanosheet structure 204; wherein the gate cut portion 1202 is further disposed between the first source/drain region 802 (left side) and the second source/drain region 802 (right side) (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
In regard to claim 16, Ando et al. teach a source/drain contact 1002 disposed on one of the first source/drain region 802 (left side) and the second source/drain region 802 (right side), wherein part of the gate cut portion 1202 contacts the source/drain contact 1002 (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
In regard to claim 17, Ando et al. teach a cap layer 906 disposed on the first gate region 904 (left side), the second gate region 904 (right side) and the gate cut portion 1202, wherein the cap layer 906 contacts the gate cut portion 1202 (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 2008/0283937 A1) as applied to claims 1-5, 8 and 18-20 above, and further in view of Ando et al. (US 2019/0157414 A1).
Shin teaches all mentioned in the rejection above.
However, Shin fails to teach a spacer layer disposed between the isolation region and the part of the gate cut portion.
In regard to claim 9, Ando et al. teach a spacer layer 208 disposed between the isolation region (region between 208) and the part of the gate cut portion 1202 (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure as taught by Shen with the semiconductor device having a spacer layer disposed between the isolation region and the part of the gate cut portion as taught by Ando et al. to reduce parasitic capacitance (page 1, paragraph [0002]).
In regard to claim 10, Ando et al. teach the part of the gate cut portion 1202 disposed in the isolation region comprises a pinched-off portion 804 of the dielectric liner layer (in 1202) (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
In regard to claim 11, Ando et al. teach a cap layer 906 disposed on the first gate region 904 (left side), the second gate region 904 (right side) and the gate cut portion 1202, wherein the cap layer 906contacts the gate cut portion 1202 (Figures 2-12, pages 2-4, paragraphs [0023]-[0049]).
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following patents are cited to further show the state of the art with respect to semiconductor devices:
Ando et al. (US 2020/0111886 A1) Brazzelli et al. (US 2007/0184615 A1)
Cheng et al. (US 9,362,355 B1) Fan et al. (US 12,363,988 B2)
Frougier et al. (US 2020/0152504 A1) Jung et al. (US 11,211,456 B2)
Jung et al. (US 11,843,053 B2) Kang et al. (US 2012/0074484 A1)
Matsuoka et al. (US 2009/0001444 A1) Wang et al. (US 12,218,214 B2)
Wu et al. (US 12,191,379 B2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm.
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IMS
February 3, 2026
/IDA M SOWARD/Primary Examiner, Art Unit 2898