DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
The Examiner acknowledges the applicant's submission of the amendment dated 10/29/25, which has been entered.
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statements, dated 7/29/25 and 9/2/25, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4-10, 12, and 14-18 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over Luukkainen (US 20100312947) in view of Moll (US 7533242).
With respect to claim 2, the Luukkainen reference teaches a memory module comprising:
a control module; (e.g. fig. 2, control 22)
a non-volatile memory (e.g. fig. 2, non-volatile mass memory 26) that is readable and writable by the control module; (paragraph 44, where mass storage memory device 20 will receive an allocation of host memory to store contents of the volatile RAM 24, in general the allocation may be for storing data for any read/write memory contained within the mass storage memory device 20; paragraph 38, where mass storage memory 20 includes a microcontroller or, more simply, a controller 22 that is connected via at least one internal bus 27 with a volatile RAM 24, a non-volatile mass memory 26 (e.g., a multi-gigabyte flash memory mass storage) and a MSMB interface (I/F) 28) and
an interface (see fig. 2, interface 28) for connecting the memory module and the control module to a host device be separate from the memory module, (paragraph 38, where mass storage memory 20 includes a microcontroller or, more simply, a controller 22 that is connected via at least one internal bus 27 with a volatile RAM 24, a non-volatile mass memory 26 (e.g., a multi-gigabyte flash memory mass storage) and a MSMB interface (I/F) 28) wherein the host device includes system memory having a first location and a second location of the system memory of the host device allocated for use by the memory module, the system memory including random access memory, (paragraph 18, where the host device 10 may allocate RAM 14 dynamically and pass a `pointer` to the allocated RAM to the mass storage memory device 20. It is then up to the controller 22 of the mass storage memory device 20 how to utilize the allocated host RAM 14 [i.e. there is a host portion and a mass storage memory utilized in host RAM 14])
the control module configured to:
receive, from the host device and via the interface, a command for reading data from the non-volatile memory; (paragraph 41, where mass storage memory device 20 may store, for example, large tables into the RAM 14 using a RAM WRITE command (a newly specified command), or it may fetch data from the host device RAM 14 using a RAM READ command (another newly specified command))
and wherein system memory that is accessible by the control module of the memory module. (paragraph 41, where mass storage memory device 20 may store, for example, large tables into the RAM 14 using a RAM WRITE command (a newly specified command), or it may fetch data from the host device RAM 14 using a RAM READ command (another newly specified command); and paragraph 43, where the controller 22 of the mass storage memory device 20 how to utilize the allocated host RAM 14)
However, the Luukkainen reference does not explicitly teach to determine, in response to the command, that the data is stored in the second location of the system memory; and initiate, based at least in part on the data being stored in the second location of the system memory and the command, copying the data from the second location of the system memory to the first location of the system memory; and the RAM is a DRAM.
The Moll reference teaches it is conventional to:
determine, in response to the command, that the data is stored in the second location of the system memory; (column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches, according to various embodiments; and column 11, lines 24-45, where a one-dimensional stride hint is provided for patterns where memory locations are accessed in a sequence where two locations accessed consecutively are separated by a fixed interval [i.e. data can be moved/copied from L2 to L1 in response to an ‘access pattern’ which includes read commands])
initiate, based at least in part on the data being stored in the second location of the system memory and the command, copying the data from the second location of the system memory to the first location of the system memory; (column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches, according to various embodiments [i.e. data can be moved/copied from L2 to L1 in response to ‘access pattern’ which includes read commands])
and for the RAM to be a DRAM. (column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches)
It would have been obvious to a person of ordinary skill in the art at the time of invention to modify the Luukkainen reference to have determine, in response to the command, that the data is stored in the second location of the system memory; and initiate, based at least in part on the data being stored in the second location of the system memory and the command, copying the data from the second location of the system memory to the first location of the system memory; and for the RAM to be a DRAM, as taught by the Moll reference.
The suggestion/motivation for doing so would have been to provide any combination of parameters describing a memory reference traffic pattern to search for, when to begin searching, when to terminate prefetching, and how aggressively to prefetch; and thus the hardware prefetchers are enabled to make improved traffic prediction, providing more accurate results using reduced hardware resources. (Moll, abstract)
Therefore it would have been obvious to combine the Luukkainen and Moll references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 4, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the control module is further configured to send a copy command to the host device. (Moll, column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches, according to various embodiments [i.e. data can be moved/copied from L2 to L1 after a read])
With respect to claim 5, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the control module is further configured to send a RAM READ command to the host device. (Moll, column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches [i.e. data is read/written from the DRAM and caches during promotion])
With respect to claim 6, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the control module is further configured to send a RAM WRITE command to the host device to copy the data from the second location of the system memory to the first location of the system memory. (Moll, column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches [i.e. data is read/written from the DRAM and caches during promotion])
With respect to claim 7, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the control module is further configured to: send, via the interface and to the host device, a second command to allocate the second location to be accessible by the memory module. (paragraph 41, where mass storage memory device 20 may store, for example, large tables into the RAM 14 using a RAM WRITE command (a newly specified command), or it may fetch data from the host device RAM 14 using a RAM READ command (another newly specified command); and paragraph 43, where the controller 22 of the mass storage memory device 20 how to utilize the allocated host RAM 14)
With respect to claim 8, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the control module is further configured to: send, via the interface and to the host device, a second command to de-allocate the second location after initiating copying the data from the second location of the system memory to the first location of the system memory. (Moll, column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches [i.e. locations will be deallocated after moving])
With respect to claim 9, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the non-volatile memory includes at least one of embedded multi-media card (eMMC), a solid-state drive (SSD), a universal flash storage (UFS), or a micro-secure digital (microSD). (Luukkainen, paragraph 37, where MSMB 18 may be compatible with any suitable mass memory interface standard such as MMC or UFS)
With respect to claim 10, the combination of the Luukkainen and Moll references teaches the memory module of claim 2, wherein the control module is further configured to: receive, from the host device, a second command for writing second data from the system memory of the host device to the memory module, wherein the second data resides in the first location of the system memory; initiate writing of the second data from the first location of the system memory to the second location of the system memory; and initiate writing the second data from the second location of the system memory to the non-volatile memory. (Moll, column 9, lines 10-37, where the memory elements may be promoted from the DRAM to any of the first and second level caches, and may be promoted from the second to any of the first level caches, according to various embodiments [i.e. data can be moved/copied from one level to another])
Claims 12 and 14-18 are the method implementation of the memory module claims as shown above, and rejected under the same rationale.
Claims 3, 11, 13, and 19-21 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over the combination of the Luukkainen (US 20100312947) in view of Moll (US 7533242), as shown in the rejections above, and further view of Kaiya (US 20030028737).
With respect to claim 3, the combination of the Luukkainen and Moll references does not explicitly teach the memory module of claim 2, wherein the control module is further configured to:
send, to the host device and in response to initiating the copying of the data to the first location of the system memory of the host device, an acknowledgment indicating that the command for reading the data from the non-volatile memory has been executed.
The Kaiya reference teaches it is conventional to:
send, to the host device and in response to initiating the copying of the data to the first location of the system memory of the host device, an acknowledgment indicating that the command for reading the data from the non-volatile memory has been executed. (Kaiya, fig. 2, step S1; and paragraphs 68, 71, 113, where acknowledgement or notification that the command for writing the data to the non-volatile memory has been executed is also provided prior to actually moving said data to the non-volatile memory)
It would have been obvious to a person of ordinary skill in the art at the time of invention to modify the combination of Luukkainen and Moll references to send, to the host device and in response to initiating the copying of the data to the first location of the system memory of the host device, an acknowledgment indicating that the command for reading the data from the non-volatile memory has been executed, as taught by the Kaiya reference.
The suggestion/motivation for doing so would have been to provide a logical-disk copying method, disk-storage system and storage medium that can be accessed immediately in the copy complete state according to a copy instruction even though copying real data. (Kaiya, paragraph 25)
Therefore it would have been obvious to combine the Luukkainen, Moll, and Kaiya references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 11, the combination of the Luukkainen and Moll references does not explicitly teach the memory module of claim 10, wherein the control module is further configured to: send, in response to the writing of the second data from the first location in the system memory of the host device to the second location in the system memory of the host device and without first initiating writing the second data into the memory of the memory module, an acknowledgment indicating that the command for writing the second data from the system memory of the host device to the memory module has been executed.
The Kaiya reference teaches it is conventional to:
send, in response to the writing of the second data from the first location in the system memory of the host device to the second location in the system memory of the host device and without first initiating writing the second data into the memory of the memory module, an acknowledgment indicating that the command for writing the second data from the system memory of the host device to the memory module has been executed. (Kaiya, fig. 2, step S1; and paragraphs 71 & 113, where acknowledgement or notification that the command for writing the data to the non-volatile memory has been executed is also provided prior to actually moving said data to the non-volatile memory)
It would have been obvious to a person of ordinary skill in the art at the time of invention to modify the combination of Luukkainen and Moll references to send, in response to the writing of the second data from the first location in the system memory of the host device to the second location in the system memory of the host device and without first initiating writing the second data into the memory of the memory module, an acknowledgment indicating that the command for writing the second data from the system memory of the host device to the memory module has been executed, as taught by the Kaiya reference.
The suggestion/motivation for doing so would have been to provide a logical-disk copying method, disk-storage system and storage medium that can be accessed immediately in the copy complete state according to a copy instruction even though copying real data. (Kaiya, paragraph 25)
Therefore it would have been obvious to combine the Luukkainen, Moll, and Kaiya references for the benefits shown above to obtain the invention as specified in the claim.
Claim 13 is the method implementation of the memory module claims as shown above, and rejected under the same rationale.
Claims 19-21 are the host device implementation of the memory module claims as shown above, and rejected under the same rationale. The Examiner further notes claims 2 and 4-10 to teach other limitations within the claims as well.
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 8-15 of the remarks) and amendments with respect to claims 2-21 have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the Luukkainen reference to teach the newly amended claim language as shown in the updated rejections above.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137