DETAILED ACTION
This Office action is in response to the application and preliminary amendment filed on 13 October 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claim 15 is objected to because of the following informalities:
At lines 17-19, claim 15 recites “a sixth switch of the first switching leg is coupled between the fourth node and a ninth node”. It is evident, based on Applicant’s disclosure, that “fourth node” in this limitation should be changed to fifth node, because immediately above the quoted recitation, claim 15 recites that the fifth switch of the first switching leg is coupled between the fourth node and an eight node. Thus it is clear that the sixth switch of the first switching leg is the switch that is coupled between the fifth node and the ninth node.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “a fourth duration” at line 3. However, claim 2 (from which claim 3 depends) already introduces first, second, third and fourth durations, leaving it unclear if claim 3 is referring back to the fourth duration or if it is intending to introduce a fifth duration. For purposes of examination, “a fourth duration” in claim 3 is being interpreted as a fifth duration.
Similarly, claim 4, which depends from claim 3, recites “a fifth duration” at line 3. For purposes of examination, “a fifth duration” in claim 4 is being interpreted as a sixth duration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-14 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Woywode et al. (US 2014/02415071; hereinafter “Woywode”).
In re claims 1 and 19, Woywode discloses an inverter (Fig. 2) configured for a wireless power system ([0035], [0038]: power is coupled wirelessly through transformer 28), the inverter comprising:
at least one capacitor (Fig. 2: Cz1, Cz2, Ssn,1 etc.); and
at least one switching leg (S1-S4 and/or S5-S8), each switching leg including a plurality of switches having at least one switch coupled to the at least one capacitor (S1-S4 and/or S5-S8 are all coupled to the capacitors in Fig. 2), wherein the plurality of switches of each switching leg are configured to be controlled such that, during operation:
an output voltage is produced, the output voltage having an asymmetric multilevel profile with at least four non-zero unequal voltage levels (Fig. 4 and [0063]: asymmetric multilevel waveform as shown having non-zero levels of Uz, Uz/2, -Uz/2 and -Uz); and
at least one switch of the plurality of switches operates with zero-voltage switching (Figs. 3, 4 and [0058]).
In re claims 2 and 20, Woywode discloses wherein the plurality of switches of each switching leg are configured to be controlled such that, during operation:
at least one switch of the plurality of switches is operated to transition from a minimum voltage level of the output voltage to a maximum voltage level of the output voltage by providing a first non-zero voltage level for a first duration and a second non-zero voltage level for a second duration (Figs. 3, 4: with the understanding that only one cycle of a repeating, periodic switching waveform is shown, switching occurs from the minimum voltage level of -Uz to the maximum voltage level of +Uz (in the second switching cycle, not shown) by providing a first non-zero voltage level of -Uz/2 for a first duration and a second non-zero voltage level of +Uz/2 for a second duration; see annotated Fig. 4 of Woywode, below); and
at least one switch of the plurality of switches is operated to transition from the maximum voltage level of the output voltage to the minimum voltage level of the output voltage by providing the first non-zero voltage level for a third duration and the second non-zero voltage level for a fourth duration (Figs. 3, 4: the switching waveform transitions from maximum voltage of +Uz to minimum voltage of -Uz by providing the first non-zero voltage level of -Uz/2 for a third duration and the second non-zero voltage level of +Uz/2 for a 4th duration; see annotations below), wherein the first and third durations and/or the second and fourth durations have different lengths (see annotated Fig. 4 below: 1st and 3rd durations are unequal and 2nd and 4th durations are unequal).
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Fig. 4 of Woywode, annotated by the examiner
In re claim 3, Woywode discloses wherein transitioning from the minimum voltage level of the output voltage to the maximum voltage level of the output voltage includes operating at least one switch of the plurality of switches to provide a zero voltage level for a
In re claim 4, Woywode discloses wherein transitioning from the maximum voltage level of the output voltage to the minimum voltage level of the output voltage includes operating at least one switch of the plurality of switches to provide the zero voltage level for a
In re claim 5, Woywode discloses at least one input configured to receive an input voltage Vdc (Fig. 2: voltage along top-most voltage rail of the circuit, corresponding to voltage Uz).
In re claim 6, Woywode discloses wherein the minimum voltage level is -Vdc, the first non-zero voltage level is -Vdc/n, the second non-zero voltage level is +Vdc/n, and the maximum voltage level is +Vdc, wherein n is a positive integer equal to or greater than two (see Figs. 3-4, where voltage Uz corresponds to the claimed Vdc and n=2).
In re claim 7, Woywode discloses wherein the multilevel profile comprises at least five distinct voltage levels comprising the minimum voltage level of -Vdc, the first non-zero voltage level of -Vdc/2, a zero voltage level, the second non-zero voltage level of +Vdc/2, and the maximum voltage level +Vdc (see Figs. 3-4, where voltage Uz corresponds to the claimed Vdc).
In re claim 9, Woywode discloses wherein the plurality of switches of each switching leg comprises a first switch, a second switch, a third switch, and a fourth switch (Fig. 2: S1-S4, D1, D2 and/or S5-S8, D3, D4).
In re claim 10, Woywode discloses wherein the at least one capacitor comprises (i) a first capacitor coupled between a first node and a second node and (ii) a second capacitor coupled between the second node and a third node, wherein the first switch of the switching leg is coupled between the first node and a fourth node, the second switch of the switching leg is coupled between the fourth node and the third node, wherein the third switch of the switching leg and the fourth switch of the switching leg are coupled between the second node and the fourth node, wherein a source of the third switch of the switching leg is connected to the source of the fourth switch of the switching leg, and wherein the first node and the third node are inputs to the inverter (see annotated Fig. 2 of Woywode, below, showing 1st and 2nd capacitors, 1st-4th switches, 1st-4th nodes).
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Fig. 2 of Woywode, annotated for claim 10
In re claim 11, Woywode discloses wherein the first switch of the switching leg is coupled between a first node and a second node, the second switch of the switching leg is coupled between the second node and a third node, the third switch of the switching leg is coupled between the third node and a fourth node, and the fourth switch of the switching leg is coupled between the fourth node and a fifth node, wherein the capacitor is coupled between the second node and the fourth node, and wherein the first node and the fifth node are inputs to the inverter (see annotated Fig. 2 below, showing 1st-4th switches, 1st-5th nodes and capacitor).
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Fig. 2 of Woywode, annotated for claim 11
In re claim 12, Woywode discloses wherein the at least one capacitor comprises (i) a first capacitor coupled between a first node and a second node and (ii) a second capacitor coupled between the second node and a third node, wherein the first switch of the switching leg is coupled between the first node and a fourth node, the second switch of the switching leg is coupled between the fourth node and a fifth node, the third switch of the switching leg is coupled between the fifth node and a sixth node, and the fourth switch of the switching leg is coupled between the sixth node and the third node, wherein a first device is coupled between the second node and the fourth node, and a second device is coupled between the second node and the sixth node, and wherein the first node and the third node are inputs to the inverter (see annotated Fig. 2, below, showing 1st-2nd capacitors, 1st-4th switches, 1st-6th nodes, 1st-2nd devices).
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Fig. 2 of Woywode, annotated for claims 12-14
In re claims 13-14, Woywode discloses wherein the first and second devices are diodes and switches (see annotated Fig. 2, above, noting that diodes are themselves a type of switch).
In re claim 16, Woywode discloses wherein the at least one capacitor comprises (i) a first capacitor coupled between a first node and a second node, (ii) a second capacitor coupled between the first node and a third node, and (iii) a third capacitor coupled between the second node and the third node, wherein the first switch of a first switching leg is coupled between the first node and a fourth node, the second switch of the first switching leg is coupled between the fourth node and the third node, the third switch of the first switching leg is coupled between the third node and a fifth node, and the fourth switch of the first switching leg is coupled between the fifth node and the second node, wherein the first switch of a second switching leg is coupled between the first node and a sixth node, the second switch of the second switching leg is coupled between the sixth node and the third node, the third switch of the second switching leg is coupled between the third node and a seventh node, and the fourth switch of the second switching leg is coupled between the seventh node and the second node, and wherein the first node and the second node are inputs to the inverter (in Fig. 1 of Woywode: 1st capacitor is 22, connected between 1st and 2nd nodes being the upper and lower DC rails; further, see annotated Fig. 2 of Woywode, below, showing 1st-4th switches of 1st switching leg (S1, D1, D2, S4), 1st-4th switches of 2nd switching leg (S5, D3, D4, S8), 1st-7th nodes, 2nd-3rd capacitors).
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Fig. 2 of Woywode, annotated for claim 16
In re claim 17, Woywode discloses wherein the inverter is a half-bridge inverter (Fig. 2: e.g., the first switching leg of S1-S4, D1-D2 forms an NPC half-bridge inverter).
In re claim 18, Woywode discloses wherein the inverter is a full-bridge inverter (Fig 2: the two switching legs including S1-S8, D1-D4 form an NPC full-bridge inverter).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woywode.
In re claim 8, Woywode discloses the invention as explained above, except for wherein each switch of the plurality of switches is an N-channel MOSFET.
However, the use of MOSFETs, including N-channel MOSFETs as power semiconductor switching elements in the power conversion field, such as in inverters like that of Woywode, was ubiquitously well-known in the art. Power MOSFETs were widely used in such applications due to their low relative cost, broad availability, and favorable performance characteristics such as high switching frequency and high voltage/power ratings.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the inverter of Woywode by using N-channel MOSFETs for each switch of the plurality of switches because of their low relative cost, wide availability, and favorable performance characteristics such as high switching frequency and high voltage/power ratings.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woywode in view of Huang et al. (US 2020/0099313; hereinafter “Huang”).
In re claim 15, Woywode discloses wherein the at least one capacitor comprises (i) a first capacitor coupled between a first node and a second node (Fig. 1: 1st capacitor 22 coupled between maximum and minimum DC voltages), (ii) a second capacitor coupled between the first node and a third node (Fig. 2: upper capacitor Uz/2), and (iii) a third capacitor coupled between the second node and the third node (Fig. 2: lower capacitor Uz/2).
Woywode does not disclose wherein the first switch of a first switching leg is coupled between the first node and a fourth node, the second switch of the first switching leg is coupled between the fourth node and the third node, the third switch of the first switching leg is coupled between the third node and a fifth node, and the fourth switch of the first switching leg is coupled between the fifth node and the second node, wherein the first switch of a second switching leg is coupled between the first node and a sixth node, the second switch of the second switching leg is coupled between the sixth node and the third node, the third switch of the second switching leg is coupled between the third node and a seventh node, and the fourth switch of the second switching leg is coupled between the seventh node and the second node, wherein a fifth switch of the first switching leg is coupled between the fourth node and an eighth node, a fifth switch of the second switching leg is coupled between the seventh node and the eighth node, a sixth switch of the first switching leg is coupled between the fourth node and a ninth node, and a sixth switch of the second switching leg is coupled between the sixth node and the ninth node, and wherein the first node and the second node are inputs to the inverter.
Whereas Huang discloses a stacked full-bridge inverter having the above features from claim 15 (see partial reproduction of Fig. 6 of Huang, below, annotated to show 1st-9th nodes, 1st-6th switches of 1st switching leg (comprising Q1-Q4, Q14, Q15) and 1st-6th switches of 2nd switching leg (comprising Q5-Q8, Q13, Q16)).
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Portion of Fig. 6 of Huang, annotated for claim 15
Huang teaches that this circuit provides a multi-level inverter topology with reduced circuit complexity and requiring lower voltage-rated transistors ([0006], [0009]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the inverter of Woywode to use the topology taught in Huang as explained above, in order to provide for a multi-level inverter with reduced complexity and enabling the use of lower withstand voltage rated devices, as taught by Huang.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woywode in view of Weidner et al. (US Patent 10,680,4572; hereinafter “Weidner”).
In re claims 21 and 22, Woywode discloses the invention as explained above, except for wherein the inverter is disposed within a wall box and wherein an output of the inverter is connected to the impedance matching network via a cable; and/or, wherein the inverter is disposed within a charging pad configured to be positioned under a vehicle and wherein an input to the inverter is connected to a cable.
Whereas Weidner discloses wireless power transfer systems for electric vehicle charging (Fig. 1), in which a transmitting inverter is disposed either within a wall box (130: a load or distribution center is understood as encompassing a “wall box”) or within a charging pad base (102a) and routing power via a cable (110; noting from col 4: 39-57 that the wall box 130 may output either DC or AC through a cable, indicating the alternative placements of the inverter).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the inverter of Woywode in such a way that the inverter is disposed within a wall box and wherein an output of the inverter is connected to the impedance matching network via a cable; and/or, wherein the inverter is disposed within a charging pad configured to be positioned under a vehicle and wherein an input to the inverter is connected to a cable, as shown and taught by Weidner. Such modification and intended usage represent a known and conventional use for the inverter of Woywode to achieve a known and desirable effect—charging of an electric vehicle/battery through wireless/non-contact power transfer as taught by Weidner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2020/0280267 discloses a Single-Phase Multi-Level Asymmetric Inverter With AC-Bypass And Asymmetric Modulation Strategy.
US Patent 11,646,671 discloses an Unfolder-based Single-stage AC-AC Conversion System.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 Cited by Applicant in the 06 December 2024 Information Disclosure Statement.
2 Cited by Applicant in the 06 December 2024 Information Disclosure Statement.
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