DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ebata et al. (US 2012/0212362).
Regarding claim 1, Ebata et al. discloses a semiconductor integrated circuit in figure 2 that teaches: a terminal (Vb); an internal resistor that is either a pull-up resistor (MPu, is a PMOS which act like pull-up resistor) including a first end which is connected to the terminal (Vb) and a second end to which a first constant voltage is applied (VCCA) or a pull-down resistor (MNd, is a NMOS which act like pull-down resistor) including a first end which is connected to the terminal (Vb) and a second end to which a ground voltage (VSSA) is applied; and an AD converter (ADC) configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more (D0, D1, …. Dn-1, see para. 0059, line 1) (see figure 2, and its descriptions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 2009/0000375) and further in view of Otsuka et al. (USP 6, 963,298).
Regarding claim 1, Johnson et al. discloses an architecture in figure 2 that teaches: a terminal (44); an internal resistor (42) that is either a pull-up resistor (para. 0019, line 2 and para. 0029, line 2) including a first end which is connected to the terminal (44) and a second end to which a first constant voltage (50) is applied or a pull-down resistor including a first end which is connected to the terminal and a second end to which a ground voltage is applied; and an AD converter (40) configured so that a voltage of the terminal (Vs) is converted into digital data (58) (see figure 2 and its descriptions).
Johnson fails to mention the digital data having a number of bits of 2 or more.
While, Otsuka discloses an ADC architecture in figure 1 that teaches multiple digital output (b0, b1, ….bn-1).
Therefore, it would have been obvious to an ordinary skill in the art at the time of effective filling of the invention to implement ADC architecture teach by Otsuka into Johnson’s ADC to output multi-bit digital data.
Regarding claim 3 Otsuka discloses an ADC architecture in figure 1 that teaches: AD converter includes: a resistor ladder circuit configured to generate a plurality of reference voltages; a plurality of comparators configured to compare the voltage of the terminal and each of the plurality of reference voltages; and an encoder configured to convert each of outputs of the plurality of comparators into the digital data (see figure 1 and its descriptions).
Regarding claim 4, Johnson teaches in figure 2 that the same constant voltage applied to pull-up resistor (42) and the ADC (40) (which is resistor ladder teach by Otsuka).
Regarding claim 5, Johnson teaches in figure 2 a internal resistor (48) is pull-down resistor (if a resistor connected to ground (52) is a pull-down resistor), the pull-up resistor (42) is connected to the terminal (44) and the first constant voltage (46) and second constant voltage (50) applied to ADC (first end of the resistor ladder, part of ADC) have the same voltage value.
Regarding claim 6, Johnson teaches in figure 2, the terminal (44) is coupled to ADC (40), if a predetermined voltage is applied to the terminal (44), the encoder (part of ADC (40)) is configured to output a signal corresponding to the predetermined voltage.
Regarding claim 7, Johnson teaches in figure 2, the terminal (44) is coupled to ADC (40) and ground voltage (52), if the ground voltage is applied to the terminal, the encoder (part of ADC(40)) is configured to output a signal corresponding to the ground voltage.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ebata et al. as applied to claim 1 above, and further in view of Otsuka et al. (USP 6, 963,298).
Regarding claim 3, Ebata fails to teach: wherein the AD converter includes: a resistor ladder circuit configured to generate a plurality of reference voltages; a plurality of comparators configured to compare the voltage of the terminal and each of the plurality of reference voltages; and an encoder configured to convert each of outputs of the plurality of comparators into the digital data.
While, Otsuka discloses an ADC architecture in figure 1 that teaches: AD converter includes: a resistor ladder circuit configured to generate a plurality of reference voltages; a plurality of comparators configured to compare the voltage of the terminal and each of the plurality of reference voltages; and an encoder configured to convert each of outputs of the plurality of comparators into the digital data (see figure 1 and its descriptions).
Therefore, it would have been obvious to an ordinary skill in the art at the time of effective filling of the invention to implement ADC architecture teach by Otsuka into Ebata’s ADC to satisfy the need of the invention.
Claim 9 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 2009/0000375) and further in view of Otsuka et al. (USP 6, 963,298) and Zawacki et al. (US 2011/0048106).
Regarding claim 9, Johnson et al. discloses an architecture in figure 2 that teaches: a terminal (44); an internal resistor (42) that is either a pull-up resistor (para. 0019, line 2 and para. 0029, line 2) including a first end which is connected to the terminal (44) and a second end to which a first constant voltage (50) is applied or a pull-down resistor including a first end which is connected to the terminal and a second end to which a ground voltage is applied; and an AD converter (40) configured so that a voltage of the terminal (Vs) is converted into digital data (58) (see figure 2 and its descriptions).
Johnson fails to mention the digital data having a number of bits of 2 or more.
While, Otsuka discloses an ADC architecture in figure 1 that teaches multiple digital output (b0, b1, ….bn-1).
Therefore, it would have been obvious to an ordinary skill in the art at the time of effective filling of the invention to implement ADC architecture teach by Otsuka into Ebata’s ADC to provide multi-bit output.
Otsuka discloses an ADC architecture in figure 1 that teaches: AD converter includes: a resistor ladder circuit configured to generate a plurality of reference voltages; a plurality of comparators configured to compare the voltage of the terminal and each of the plurality of reference voltages; and an encoder configured to convert each of outputs of the plurality of comparators into the digital data (see figure 1 and its descriptions).
However, both Johnson and Otsuka fail to teach or suggest a filter circuit in between the terminal (44) and ADC (40).
While Zawacki discloses an architecture in figure 5 that teaches a filter circuit (508) is in between the terminal (point between pull-up resistor (504) and full-down resistor (506) and the ADC (510).
Therefore, it would have been obvious to an ordinary skill in the art at the time of effective filling of the invention to implement Zawacki teaching filter circuit (508) into Johnson and Otsuka’ discloses to satisfy invention needed.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individual or in combination, fails to fairly teach or suggest objected features, which is: wherein the internal resistor is configured to be trimmable, and wherein the device further comprises: a nonvolatile storage part configured to store trimming setting.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individual or in combination, fails to fairly teach or suggest objected features, which is: wherein each of the plurality of comparators is a chopper type comparator, and the device further comprises: a bootstrap circuit configured to supply a boot voltage to a gate of a switch which is an NMOS transistor provided in the chopper type comparator.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845