DETAILED ACTION
Claim Objections
Claims 7, 15 and 19 are objected to because of the following informalities:
Regarding Claim 7:
In Line 7, “first and second terminals of the test device” already has antecedent basis.
In Line 20, the Examiner suggests amending the limitation to “fourth impedances”.
In Line 21, “a semiconductor wafer” already has antecedent basis.
Regarding Claim 15:
In Line 5, “first and second terminals of the test device” already has antecedent basis.
In Line 14, the Examiner suggests amending the limitation to “fourth impedances”.
Regarding Claim 19, the Examiner suggests amending the limitation to “fourth impedances”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 7:
In Line 6, “the second terminal of the first monitor structure” has no antecedent basis.
In Line 10, “the second terminal of the second monitor structure” has no antecedent basis.
Claims 8-14 are rejected as depending on Claim 7.
Regarding Claim 15:
In Line 4, “the second terminal of the first monitor structure” has no antecedent basis.
In Line 7, “the second terminal of the second monitor structure” has no antecedent basis.
Claims 16-20 are rejected as depending on Claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nandakumar et al. (US 6,150,669, Pub Nov 21, 2000, herein Nandakumar).
Regarding Claim 1, Nandakumar teaches:
A semiconductor wafer (Test structures are placed in the scribe lines of a wafer [2:65-3:5]. A first test structure is used, and a second test structure may be used in conjunction with the first test structure [2:11-18].), comprising:
a first monitor structure (First test structure 40) in a scribe line adjacent to a die (The test structures are placed in a scribe line of a wafer [2:65-3:5]; Fig 5) and including a first source region (Source 48), a first drain region (Drain 50), and a first gate region (Gate line 42), wherein the first gate region (42) comprises a first elongated finger extending longitudinally between the first source region (48) and the first drain region (50), as viewed from a top plan view (see [3:12-25] Fig 4); and
a second monitor structure (Second test structure 90) in the scribe line adjacent to the die (The test structures are placed in a scribe line of a wafer [2:65-3:5]; Fig 8) and including one or more second source regions (half of the source/drain regions 75 are source regions), one or more second drain regions (the other half of the source/drain regions 75 are drain regions), and a plurality of second gate regions (mesh gate structure 92 defines a plurality of gate regions), wherein each of the second gate regions (92) comprises a second elongated finger extending longitudinally over a respective region of the die between the one or more second source (75) regions and the one or more second drain regions (75), as viewed from the top plan view (see [4:22-5:2] Fig 8).
Regarding Claim 2, Nandakumar teaches:
a third monitor structure (another iteration of second test structure 90; [5:3-11]) in the scribe line adjacent to the die (The test structures are placed in a scribe line of a wafer [2:65-3:5]; Fig 8) and including one or more third source regions (half of the source/drain regions 75 are source regions), one or more third drain regions (the other half of the source/drain regions 75 are drain regions), and a plurality of third gate regions (mesh gate structure 92 defines a plurality of gate regions), wherein each of the third gate regions (92) comprises a third elongated finger extending longitudinally over a respective region of the die between the one or more third source regions (75) and the one or more third drain regions (75), as viewed from the top plan view (see [4:22-5:2] Fig 8).
Regarding Claim 3, Nandakumar teaches:
the second monitor structure is configured to represent a respective transistor on the die (Test structure 90 is a transistor [2:65-3:7]).
Regarding Claim 4, Nandakumar teaches:
the respective transistor on the die of the semiconductor wafer is a laterally-diffused metal-oxide semiconductor (LDMOS) (Figures 4 and 8 show LDMOS transistors [3:12-25],[4:22-5:2]. The test structures in Figures 4 & 8 are formed using the same process steps as the IC to as closely match the IC structures (i.e., transistors) as possible [3:5-7].).
Regarding Claim 5, Nandakumar teaches:
the first or second monitor structure is configured to have the same ON-resistance between respective source and drain regions as the respective transistor on the die (Figures 4 and 8 show transistors [3:12-25],[4:22-5:2]. The test structures in Figures 4 & 8 are formed using the same process steps as the IC to as closely match the IC structures (i.e., transistors) as possible [3:5-7].).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nandakumar in view of Se-young et al. (JP 2009027169 A, Pub Feb 5, 2009, herein Se-young).
Regarding Claim 6, Nandakumar teaches:
an arrangement of electrically conductive pads and traces in the scribe line and exposed on a surface of the semiconductor wafer, wherein the pads are coupled to respective gate regions (Gate line 42 is connected to probe pads 52 through conductive traces [3:30-35].; Fig 4)
the pads are coupled to respective source and drain regions.
Nandakumar does not teach:
the pads are coupled to respective source and drain regions.
However, Se-young teaches:
the pads are coupled to respective source and drain regions (In scribe lane region 110, source pad 192 and drain pad 194 are connected to source region 156 and drain region 158, respectively.; see Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Nandakumar in view of Se-young by having the pads are coupled to respective source and drain regions because it is applying a known technique to a known device ready for improvement to yield the predictable result of allowing the nodes of a transistor to be probed more easily.
Allowable Subject Matter
Claims 7-20 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 7, the prior art of record fails to teach or suggest, singly or in combination a system comprising:
“a sensor configured to measure:
a first impedance between first and second terminals of a test device, wherein the first impedance represents an impedance of a first monitor structure in a scribe line of a semiconductor wafer responsive to applying a first bias voltage across a third terminal and the second terminal of the first monitor structure;
a second impedance between first and second terminals of the test device, wherein the second impedance represents an impedance of a second monitor structure in the scribe line of the semiconductor wafer responsive to applying the first bias voltage across a third terminal and the second terminal of the second monitor structure;
a third impedance between the first and second terminals of the test device, wherein the third impedance represents an impedance of the first monitor structure responsive to applying a second bias voltage across the third and second terminals of the first monitor structure;
a fourth impedance between the first and second terminals of the test device, wherein the fourth impedance represents an impedance of the second monitor structure responsive to applying the second bias voltage across the third and second terminals of the second monitor structure; and
a processor configured to calculate a device impedance based on the first, second, third, and fourth impedance, wherein the device impedance is representative of an impedance of a transistor on a die of a semiconductor wafer adjacent to the scribe line” in combination with the other limitations of the Claim.
Regarding Claim 15, the prior art of record fails to teach or suggest, singly or in combination a system comprising:
“measuring a first impedance between first and second terminals of a first monitor structure in a scribe line of a semiconductor wafer responsive to applying a first bias voltage across a third terminal and the second terminal of the first monitor structure;
measuring a second impedance between first and second terminals of a second monitor structure in the scribe line of the semiconductor wafer responsive to applying the first bias voltage across a third terminal and the second terminal of the second monitor structure;
measuring a third impedance between the first and second terminals of the first monitor structure responsive to applying a second bias voltage across the third and second terminals of the first monitor structure;
measuring a fourth impedance between the first and second terminals of the second monitor structure responsive to applying the second bias voltage across the third and second terminals of the second monitor structure; and
calculating a device impedance based on the first, second, third, and fourth impedance” in combination with the other limitations of the Claim.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nandakumar (US 6,150,669) teaches the measurement of resistances of transistor structures in the gate line of a wafer. However, Nandakumar does not teach the measurement of resistances across multiple terminals of the transistor. Nandakumar also does not teach the measurement of resistances at different bias voltages. Nandakumar also does not teach using four impedances to determine a device impedance.
Conclusion
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/R.M/Examiner, Art Unit 2858 04/06/2026
/A.A/Primary Examiner, Art Unit 2858
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