DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicant’s arguments filed on 01/05/2025 have been considered but are moot in view of grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16,17,18 and 21 are rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604) in view of McLaren et al (WO 2010/128958 A1).
Regarding claim 16, Morrow discloses a server system comprising one or more optical devices configured for use in the server system, (Multiprocessor architectures may be implemented to realize network processors, web servers, database servers, see paragraph 2) at least one optical device of the one or more optical devices comprising: a processor configured to process one or more computer-readable instructions ;(microprocessor 205 for processing the one or more computer-readable instructions, see figure 5), local memory component associate with and optically coupled with the processor,( multiprocessor system 400 may further include shared memory 235 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4) an optical bus optically coupling the processor with the local memory component (multiprocessor system 400 may further include shared memory 235 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4) the optical bus being configured to transport the first optical signal, (optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24) read the first optical signal, (optical coupler 510 either read data from optical buses 505 or write data to optical buses 505, see paragraph 36 and figure 5) convert the first optical signal to computer-readable instructions of the one or more computer-readable instructions;(one or more electrical-to-optical ("E-O") transmitters are optically coupled to the optical bus using optical couplers. The E-O transmitters receive electrical signals from the processors and convert the electrical signals to optical signals to be guided onto the optical bus, see abstract and figure 6), and
However, Morrow does not explicitly disclose convert the one or more computer-readable instructions to the first optical signal.
In a related field of endeavor, McLaren discloses convert the one or more computer-readable instructions to the first optical signal;(the router 112, in this embodiment, includes a transceiver that converts the electronic signals into optical signals encoding the same information and sends the optical signals 124 to the optical bus 104, see page 5, lines 4-6 and figures 1,2).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the processing nodes of McLaren with Morrow to provide broadcasting of optical signals and the motivation is to provide arrangement of multiple optical buses to create scalable optical interconnect fabrics for computer systems.
Regarding claim 17, Morrow discloses the server system of claim 16 wherein one or more of the first optical signal ;(optical transceiver 700 with optical source 740for generating continuous wave (CW), see paragraph 45) and the second optical signal has a transmission characteristic, the transmission characteristic including one or more of the following: a particular frequency, a frequency hopping method, a transmission speed, a transmission grouping, a transmission on/off pattern;(a first portion of the CW optical input is provided to E-O transmitter 725 as a carrier wave on which electrical data, received from one of processors 205 via electrical input port 730, is modulated with encoded data as (0101010), see paragraph 46) a reflective property, and a transmission sequence.(Only one of the claim limitation is required to be considered by the Examiner).
Regarding claim 18, Morrow discloses the server system of claim 16 wherein the first optical signal represents a first data, wherein the second optical signal represents a second data different from the first data; (if optical bus 210 supports a WDMA protocols, then multiple O-E receivers 735 may be coupled to optical bus 210 for each wavelength and modulated with electrical data, received from one of processors 205 via electrical input port 730, is modulated (first and second optical signal corresponding to different wavelengths), see paragraphs 46 and 49 and figures 8 and 9).
Regarding claim 21, Morrow discloses the server system of claim 16 wherein the first optical signal is propagated through one or more fiber optic strands; (optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24).
Claims 19,20 and 34 are rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604) in view of McLaren et al (WO 2010/128958 A1), further in view of Tsaur et al; (US 8510271).
Regarding claim 19, the combination of Morrow and McLaren does not explicitly disclose the server system of claim 16 wherein the one or more computer-readable instructions include one or more of an encryption method, a decryption method, an algorithm, a bytecode, a computer program, a java applet, HTML code, a graphics code, a routine, a key, a formula, an indicator, a pointer, or an index.
In a related field of endeavor, Tsaur discloses the server system of claim 16 wherein the one or more computer-readable instructions include one or more of an encryption method;(computer system processor 610 coupled with the memory 620 with encryption software, column 16, line 21) a decryption method, an algorithm, a bytecode, a computer program, a java applet, HTML code, a graphics code, a routine, a key, a formula, an indicator, a pointer, or an index. (Only one of the claim limitation is required to be considered by the Examiner).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the encryption software and/or hashing software of Tsaur with Morrow and McLaren to scramble the data into an unreadable code and the motivation is to provide increased security for transmitted data.
Regarding claim 20, the combination of Morrow and McLaren does not explicitly disclose the server system of claim 16 wherein the encryption and the decryption include one or more of the following: hashing, symmetric cryptography, and asymmetric cryptography.
In a related field of endeavor, Tsaur discloses the server system of claim 16 wherein the encryption and the decryption include one or more of the following: hashing, ;(computer system processor 610 coupled with the memory 620 with hashing software, column 16, line 21) symmetric cryptography, and asymmetric cryptography. Motivation same as claim 19.
Regarding claim 34, Morrow discloses the server system of claim 16 wherein the local memory component optically coupled with the processor; (memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as local memories 405 to each of processors 205, see paragraph 34 and figure 4)
However, the combination of Morrow and McLaren does not explicitly disclose comprises Random Access Memory (RAM), static memory, SD- RAM, DDR-RAM, RAMBUS, working memory, or temporary cache memory.
In a related filed of endeavor, Tsaur discloses comprises Random Access Memory (RAM),( Memory 620 can be a random access memory (RAM), see column 16, lines 3,4 and figure 6) static memory, SD- RAM, DDR-RAM, RAMBUS, working memory, or temporary cache memory.
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the random access memory (RAM) of Tsaur with Morrow and McLaren to store the data and the motivation is to provide temporary storage of data.
Claims 22 and 24 are rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604).
Regarding claim 22, Morrow discloses an optical device configured for use in a server system, (Multiprocessor architectures may be implemented to realize network processors, web servers, database servers, see paragraph 2) the optical device comprising: a processor configured to process one or more computer-readable instructions ;(microprocessor 205 for processing the one or more computer-readable instructions, see figure 5) a local memory component optically coupled with and associated with the processor, and;( multiprocessor system 400 may further include shared memory 235 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4) an optical bus optically coupling the processor with the local memory component (multiprocessor system 400 may further include shared memory 235 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4), wherein the optical bus comprises a first optical component coupled with the processor and second optical component coupled with the local memory component (optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24 and optical coupler 510 either read data from optical buses 505 or write data to optical buses 505, see paragraph 36 and figure 5 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4) wherein the first optical component is configured to receive a first optical signal, optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24 wherein the second optical component is configured to convert from to the first optical signal (optical coupler 510 either read data from optical buses 505 or write data to optical buses 505, see paragraph 36 and figure 5).
However, Morrow does not explicitly disclose stored data it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention that the local memories 405 are coupled directly to a single processor, local memories 405 may be accessed quicker than shared memory 235 and without consuming bandwidth on optical bus 210 and thus optical signal conversion can be either from data stored from the local memory and motivation is increased processing speed.
Regarding claim 24, Morrow discloses the optical device of claim 22 wherein the optical bus is configured to transmit two or more frequencies, wherein the two or more frequencies are configured to propagate non-binary analog data; (if optical bus 210 supports a WDMA protocols, then multiple O-E receivers 735 may be coupled to optical bus 210 for each wavelength (frequency) and modulated with electrical data, (analog data) received from one of processors 205 via electrical input port 730, is modulated see paragraphs 46 and 49 and figures 8 and 9).
Claim 23 is rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604) further in view of Butcher (US 2004/0017377).
Regarding claim 23, Morrow does not explicitly disclose the optical device of claim 22 wherein the one or more computer-readable instructions include binary code.
In a related field of endeavor, Butcher discloses the optical device of claim 22 wherein the one or more computer-readable instructions include binary code; (colored filled bitmap with the binary code representing the appropriate filled color register, see paragraph 96 and figure 13).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the color bit map of Butcher with Morrow to provide one bit for each pixel of the display data and the motivation is to provide efficient structuring of the pixel data in the memory.
Claim 35 is rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604) in view of Tsaur et al; (US 8510271).
Regarding claim 35, Morrow discloses the optical device of claim 22 wherein the local memory component optically coupled with the processor comprises; (memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as local memories 405 to each of processors 205, see paragraph 34 and figure 4)
However, Morrow does not explicitly disclose Random Access Memory (RAM), static memory, SD- RAM, DDR-RAM, RAMBUS, working memory, or temporary cache memory.
In a related filed of endeavor, Tsaur discloses Random Access Memory (RAM), ( Memory 620 can be a random access memory (RAM), see column 16, lines 3,4 and figure 6) static memory, SD- RAM, DDR-RAM, RAMBUS, working memory, or temporary cache memory.
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the random access memory (RAM) of Tsaur with Morrow to store the data and the motivation is to provide temporary storage of data.
Claims 26-28,30 and 33 are rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604) view of McLaren et al (WO 2010/128958 A1).
Regarding claim 26, Morrow discloses an optical device configured for use in a server system, (Multiprocessor architectures may be implemented to realize network processors, web servers, database servers, see paragraph 2) the optical device comprising: a processor configured to process one or more computer-readable instructions;(microprocessor 205 for processing the one or more computer-readable instructions, see figure 5) a local memory component optically coupled with and associated with the processor, and;( multiprocessor system 400 may further include shared memory 235 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4) an optical bus optically coupling the processor with the local memory component (multiprocessor system 400 may further include shared memory 235 and memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as, local memories 405 to each of processors 205, see paragraph 34 and figure 4),wherein the optical bus comprises two or more first optical components, (optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24 and optical coupler 510 either read data from optical buses 505 or write data to optical buses 505, see paragraph 36 and figure 5) the two or more first optical components being configured to do one or more of the following: convert a first optical signal to computer-readable instructions of the one or more computer-readable instructions or ;(one or more electrical-to-optical ("E-O") transmitters are optically coupled to the optical bus using optical couplers. The E-O transmitters receive electrical signals from the processors and convert the electrical signals to optical signals to be guided onto the optical bus, see abstract and figure 6), and
However, Morrow does not explicitly disclose convert the one or more computer-readable instructions to the first optical signal.
In a related field of endeavor, McLaren discloses convert the one or more computer-readable instructions to the first optical signal;(the router 112, in this embodiment, includes a transceiver that converts the electronic signals into optical signals encoding the same information and sends the optical signals 124 to the optical bus 104, see page 5, lines 4-6 and figures 1,2).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the processing nodes of McLaren with Morrow to provide broadcasting of optical signals and the motivation is to provide arrangement of multiple optical buses to create scalable optical interconnect fabrics for computer systems.
Regarding claim 27, Morrow discloses the optical device of claim 26 wherein the first optical signal ;(optical transceiver 700 with optical source 740for generating continuous wave (CW), see paragraph 45) has a transmission characteristic, the transmission characteristic including one or more of the following: a particular frequency, a frequency hopping method, a transmission speed, a transmission grouping, a transmission on/off pattern ;(a first portion of the CW optical input is provided to E-O transmitter 725 as a carrier wave on which electrical data, received from one of processors 205 via electrical input port 730, is modulated with encoded data as (0101010), see paragraph 46) a reflective property, and a transmission sequence.(Only one of the claim limitation is required to be considered by the Examiner).
Regarding claim 28, Morrow discloses the optical device of claim 26 wherein the two or more first optical signal components are further configured to perform a logic operation with the first optical and a second optical signal;(optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24) wherein the first optical signal represents a first data, wherein the second optical signal represents a second data different from the first data ;(if optical bus 210 supports a WDMA protocols, then multiple O-E receivers 735 may be coupled to optical bus 210 for each wavelength and modulated with electrical data, received from one of processors 205 via electrical input port 730, is modulated (first and second optical signal corresponding to different wavelengths), see paragraphs 46 and 49 and figures 8 and 9).
Regarding claim 30, Morrow discloses The optical device of claim 26 wherein the optical bus is configured to transmit two or more frequencies, wherein the two or more frequencies are configured to propagate non-binary analog data; (if optical bus 210 supports a WDMA protocols, then multiple O-E receivers 735 may be coupled to optical bus 210 for each wavelength (frequency) and modulated with electrical data, (analog data) received from one of processors 205 via electrical input port 730, is modulated see paragraphs 46 and 49 and figures 8 and 9).
Regarding claim 33, Morrow discloses the optical device of claim 26 wherein the first optical signals propagated through one or more fiber optic strands; (optical bus 210 include medium capable of transporting optical signals therein and the optical bus 210 is a waveguide laminated into circuit board 215, see paragraph 24).
Claims 29 and 36 are rejected under 35 USC 103 as being unpatentable over Morrow et al; (US 2005/0276604) view of McLaren et al (WO 2010/128958 A1) further in view of Tsaur et al; (US 8510271).
Regarding claim 29, the combination of Morrow and McLaren does not explicitly disclose the optical device of claim 26 wherein the one or more computer-readable instructions include one or more of an encryption method, a decryption method, an algorithm, a bytecode, a computer program, a java applet, HTML code, a graphics code, a routine, a key, a formula, an indicator, a pointer, or an index.
In a related field of endeavor, Tsaur discloses the optical device of claim 26 wherein the one or more computer-readable instructions include one or more of an encryption method ;(computer system processor 610 coupled with the memory 620 with encryption software, column 16, line 21) a decryption method, an algorithm, a bytecode, a computer program, a java applet, HTML code, a graphics code, a routine, a key, a formula, an indicator, a pointer, or an index. (Only one of the claim limitation is required to be considered by the Examiner).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the encryption software and/or hashing software of Tsaur with Morrow and McLaren to scramble the data into an unreadable code and the motivation is to provide increased security for transmitted data.
Regarding claim 36, Morrow discloses the optical device of claim 26 wherein local memory component comprises; (memory controller 230 coupled to optical bus 210 to provide shared memory for all processors 205, as well as local memories 405 to each of processors 205, see paragraph 34 and figure 4)
However, Morrow does not explicitly disclose Random Access Memory (RAM), static memory, SD- RAM, DDR-RAM, RAMBUS, working memory, or temporary cache memory.
In a related filed of endeavor, Tsaur discloses Random Access Memory (RAM), ( Memory 620 can be a random access memory (RAM), see column 16, lines 3,4 and figure 6) static memory, SD- RAM, DDR-RAM, RAMBUS, working memory, or temporary cache memory.
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the random access memory (RAM) of Tsaur with Morrow to store the data and the motivation is to provide temporary storage of data.
Allowable Subject Matter
Claims 25,31 and 32 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
3. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is reproduced below.
a. Levy et al; (US 7366423) discloses a memory apparatus also includes an optical interface, and an optical-to-electrical signal converter is coupled to receive optical signals from the optical interface and provide electrical signals to the electrical device, see figure 6a.
b. Steckl et al; (US 7087281) discloses DTF optical memory making use of the property of dielectric thin film interference to create multi-color pixels and serve as a multi-level optical memory device, see figure 1.
c. Hino et al; (EP1467505 A1) discloses an illumination light source to apply light and an information-transmitting unit to transmit optical information, see figure 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMRITBIR K SANDHU whose telephone number is (571)270-1894. The examiner can normally be reached M-F 9am to 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Vanderpuye can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMRITBIR K SANDHU/Primary Examiner, Art Unit 2634
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