CTNF 18/488,307 CTNF 91098 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619(CCPA1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claim 1-20 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over of US20240137200A1 for the parent application 18/381,858 . Claim# Present application 18488307 US20240137200A1 for the application 18/381,858 Claim # 1 17 20 1.A clocking system comprising a first clock domain circuitry including a first Time of Day counter ; and second clock domain circuitry including a second counter the second clock domain circuitry configured to apply a phase adjustment signal indicative of a difference between an error measurement and a residual measured in the second counter to reduce mismatch between outputs of the first Time of Day counter and the second counter, and the error measurement representing a phase difference between the outputs of the first Time of Day counter and the second counte r 17. A network device comprising : a clocking system including first clock domain circuitry and second clock domain circuitry , the first clock domain circuitry including a first Time of Day counter and the second clock domain circuitry including a second counter , the second clock domain circuitry configured to apply a phase adjustment signal indicative of a difference between an error measurement and a residual measured in the second counter to reduce mismatch between outputs of the first Time of Day counter and the second counter, the error measurement representing a phase difference between the outputs of the first Time of Day counter and the second counter ; and a port configured to connect to a second network device, the clocking system configured to process a Time of Day timestamp received from the second network device at the port . 20. A method of Time of Day synchronization, the method comprising : receiving a Time of Day timestamp from a master network device ; and synchronizing outputs of a first Time of Day counter in a first clock domain and a second counter in a second clock domain with Time of Day timestamp based on (i) an error measurement representing a phase difference between outputs of the first Time of Day counter and the second counter and (ii) a residual measured in the second counter. 20. A clocking system comprising : first clock domain circuitry including a first Time of Day counter and a reference clock generator, the reference clock generator configured to adjust a reference clock signal based on a Time of Day timestamp to synchronize an output of the first Time of Day counter to the Time of Day timestamp; and second clock domain circuitry including a second Time of Day counter and a state machine, the state machine configured to synchronize an output of the second time of Day counter to the output of the first Time of Day counter based on (1) an error measurement representing a phase difference between outputs of the first and second Time of Day counters and (2) a residual measured in the second Time of Day counter. 11.A network device comprising : first clock domain circuitry including a first Time of Day counter and a reference clock generator, the reference clock generator configured to adjust a reference clock signal based on the Time of Day timestamp to synchronize an output of the first Time of Day counter to the Time of Day timestamp; and second clock domain circuitry including a second Time of Day counter and a state machine, the state machine configured to synchronize an output of the second time of Day counter to the output of the first Time of Day counter based on (1) an error measurement representing a phase difference between outputs of the first and second Time of Day counters and (2) a residual measured in the second Time of Day counter. a port configured to receive a Time of Day timestamp from a master network device . 1 . A method of clock domain timing synchronization, the method comprising : receiving a Time of Day timestamp from a master network device ; adjusting clock period in a first clock domain of a slave network device such that an output of first Time of Day Counter is synchronized to the Time of Day timestamp; and synchronizing an output of a second Time of Day counter in a second clock domain of the slave network device to the output of the first Time of Day counter based on (1) an error measurement representing a phase difference between outputs of the first and second Time of Day counters and (2) a residual measured in the second Time of Day counter 20 11 1 The dependent claim of the present application has double patenting with the dependent claims of the US20240137200A1 for the application 18/381858, for example: -The claim 2, of the present application, has the double patenting with the claim 4 of US20240137200A1 for the application 18/381,858. -The claim 3, of the present application, has the double patenting with the claim 2 of US20240137200A1 for the application 18/381,858. -The claim 4, of the present application, has the double patenting with the claim 11 and 5 of US20240137200A1 for the application 18/381,858, as follow: -Claim4 state “ wherein the first clock domain circuitry is configured to generate a first clock signal having an adjustable frequency for the first Time of Day counter”, has double patenting with the limitation of claim 11 : “first clock domain circuitry including a first Time of Day counter and a reference clock generator, the reference clock generator configured to adjust a reference clock signal based on the Time of Day timestamp to synchronize an output of the first Time of Day counter to the Time of Day timestamp”, and -“the second clock domain circuitry is configured to generate a second clock signal having a fixed frequency for the second counter”, has double patenting with the limitation of claim 5 : “wherein the second Time of Day counter receives a clock signal having a fixed frequency” . -The claim 5, of the present application, has the double patenting with the claim 6 of US20240137200A1 for the application 18/381,858, -The claim 6, of the present application, has the double patenting with the claim 7 of US20240137200A1 for the application 18/381,858, -The claim 8, of the present application, has the double patenting with the claim 7 of US20240137200A1 for the application 18/381,858. -The claim 9, of the present application, has the double patenting with the claim 8 of US20240137200A1 for the application 18/381,858. -The claim 10, of the present application, has the double patenting with the claim 6 of US20240137200A1 for the application 18/381,858. -The claim 11, of the present application, has the double patenting with the claim 6 of US20240137200A1 for the application 18/381,858. Thus, the claims of US20240137200A1 for the application 18/381858, contain every element of the claims, of the instant application and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. Allowable Subject Matter Claims 1-20 are allowable if the claims overcome the obviousness-type double patenting. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELTIF AJID whose telephone number is (571)272-7749. The examiner can normally be reached 9 am -5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABDELTIF AJID/ Primary Examiner, Art Unit 2478 Application/Control Number: 18/488,307 Page 2 Art Unit: 2478 Application/Control Number: 18/488,307 Page 3 Art Unit: 2478 Application/Control Number: 18/488,307 Page 4 Art Unit: 2478 Application/Control Number: 18/488,307 Page 5 Art Unit: 2478 Application/Control Number: 18/488,307 Page 6 Art Unit: 2478 Application/Control Number: 18/488,307 Page 7 Art Unit: 2478 Application/Control Number: 18/488,307 Page 8 Art Unit: 2478 Application/Control Number: 18/488,307 Page 9 Art Unit: 2478 Application/Control Number: 18/488,307 Page 10 Art Unit: 2478 Application/Control Number: 18/488,307 Page 11 Art Unit: 2478 Application/Control Number: 18/488,307 Page 12 Art Unit: 2478 Application/Control Number: 18/488,307 Page 13 Art Unit: 2478 Application/Control Number: 18/488,307 Page 14 Art Unit: 2478 Application/Control Number: 18/488,307 Page 15 Art Unit: 2478 Application/Control Number: 18/488,307 Page 16 Art Unit: 2478 Application/Control Number: 18/488,307 Page 17 Art Unit: 2478