DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08 December 2025 and 10 November 2025 has been entered.
Remarks
Claims 1-10 are pending in the application, claim 11 is canceled, and claims 12-20 are withdrawn.
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Objections
Claims 1-10 are objected to because of the following informalities:
Claims 1-10 recites various forms of “data”, such as “a first request to write data or read data”, “a second request to write data”, writing “data to the single address range”, “calculated CRC write data”, “IO write data”, “CRC read data”, and “IO read data”. Although the various forms of data do not cause any clarity issues with claim 1. The various forms do cause several clarity issues with claims 8-10 (as well 13-20 if rejoined). Accordingly, the Examiner suggests more particularly distinguishing the various forms of data such as rewriting:
“a first request to write data or read data” to:
“a first request to write IO write data or read IO read data”,
“a first request to write first write data or read first read data”.
“a second request to write data” to:
“a second request to write second data”, or
“a second request to write gaming/streaming write data”.
“calculated CRC data” to:
“calculated CRC read data” so as not to be confused with “calculated CRC write data”.
Furthermore, to conform any other recitations of “data” in the dependent claims (including the withdrawn claims) with any such potential distinguishments discussed above. Forms of data that should be distinguished throughout the claims are further illustrated in the 35 USC §112(b) rejections for recitations of data that lack clear antecedent basis further discussed below.
Claim 1 recites “memory” and then “the memory” after first reciting “a memory device”. From the specification, it appears that “the memory” recited in the claims is meant to refer back to a different memory than the “memory device”. For example, the Examiner understands “the memory device” recited in claim 1 to correspond to non-volatile memory (110) in the specification and corresponding figures, while “memory” and “the memory” correspond to volatile memory (112 or 120), controller memory buffer (122), DRAM (118), or host memory buffer (150) in host DRAM (138). Accordingly, the Examiner suggests amending the claims to clarify that writing data to “memory” or reading data from “the memory” is not writing or reading data to the “memory device”. For example, amending the claims to introduce the limitations as, “a first memory device” and “a second memory” and then making corresponding changes throughout the claims.
Claim 1 recites, “gaming or streaming operations” and “gaming/streaming operations”, which should be harmonized around one form for consistency.
Claim 2 recites, “the CRC range is a flash management unit (FMU) CRC”, which as best understood by the Examiner in light of the specification should be amended to recite, “the translated CRC address range is for a flash management unit (FMU) CRC”
Claims 3-5 and 10 recite various limitations which should be prefaced with an article (“a” or “the”) such as “dynamic random access memory (DRAM)” in claim 3, “host memory buffer (HMB)” in claim 5, and “memory” in claim 10.
Claims 2-10 are objected to for failing to correct the deficiencies of a base claim from which they depend.
Appropriate correction is required.
EXAMINER NOTE:
Although not examined, many of the withdrawn claims appear to suffer from deficiencies like those noted above and also deficiencies like those discussed in the current and previous 35 USC §112(b) rejections. The Examiner suggests reviewing these claims for precise antecedent basis and logical congruence with the claims from which they now depend. For example, the Examiner sees problematic recitations of “the data”, “the calculated CRC range”, “the read CRC range”, “the determining” “read or write requests”, “write data”, “the memory”, “the actual ECC”, “write translate the write request” “two address ranges”, “the write request”, “table and ECC”, “gaming, or tables” as well as missing articles like “an” and “the” before limitations such as “error correction code (ECC)”, or “calculated ECC” in claims 12-20.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 8:
Claim 8 recites “the data”. However. claim 1 previously recites a first request to write data or read data, a second request to write data, and writing data to the single address range. In addition claim 1 recites: “calculated CRC write data”, “IO write data”, “CRC read data”, “calculated CRC data” and “IO read data”. Accordingly, the antecedent basis of the limitation is unclear as it may find antecedent basis in any of the aforementioned data. The recitation of “the data” in claim 8 should be differentiated or claimed with particular antecedent basis to one of the previously named “data”. For example, the Examiner suggestions changing the limitation to be introduced in claim 1 according to the suggestions provided in the claim objection section above and then claimed in claim 8 as “the IO write data”, “the first write data”, “the gaming or streaming write data”, or “the second write data”.
Regarding claim 9:
Claim 9 is rejected for failing to cure the deficiencies of a rejected base claim from which it depends.
Regarding claim 10:
Claim 10 recites “the data”. However, claim 1 previously recites a first request to write data or read data, a second request to write data, and writing data to the single address range. In addition claim 1 recites: “calculated CRC write data”, “IO write data”, “CRC read data”, “calculated CRC data” and “IO read data”. Accordingly, the antecedent basis of the limitation is unclear as it may find antecedent basis in any of the aforementioned data. The recitations of “the data” in claim 10 should be differentiated or claimed with particular antecedent basis to one of the previously named “data”. For example, the Examiner suggestions changing the limitation to be introduced in claim 1 according to the suggestions provided in the claim objection section above and then claimed in claim 10 as “the IO write data”, “the first write data”, “the gaming or streaming write data”, or “the second write data”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. US 11,403,011 B1 (Gunda) in view of US Patent Application Publication No. US 2024/0329842 A1 (Pereira) in further view of US Patent Application Publication No. US 2021/0255801 A1 (Jang) in further view of US Patent Application Publication No. US 2018/0039541 A1 (Hahn) in further view of US Patent Application Publication No. US 2021/0334200 A1 (Xu) in further view of US Patent Application Publication No. US 2011/0084978 A1 (Schuette).
Regarding claim 1:
Gunda teaches a data storage device (storage device (102)), comprising: a memory device (NVM (110)); and a controller (120) coupled to the memory device (coupled to NMV (110)), wherein the controller is configured to: configure table ranges and input/output ranges for storage (by disclosing that the storage controller configures ranges and allocations of the host memory buffer for use by different modules. The different modules include address mapping tables (table ranges), which are read from the L2P mapping table (120) in the NVM (110) in memory location (114). The modules also include read/write buffers (I/O ranges) (824) for writing data to the NVM (110) [Fig. 8] [Figs. 10A-B] [Col 7: lines 21-38] [Col 16: line 49 – Col 17: line 2] [Col 21: line 16 – Col 22: line 14]) receive a first request to write data to memory or read data from the memory; wherein the first request is associated with either input/output operations, gaming/streaming operations, or table operations; determine that the first request is for the IO operations rather than for the table operations; receive a second request to write data; and write data to the memory (by disclosing that the host device (104) sends read and write requests to the storage device (102) over interface (106) to the controller (123) [Fig. 1]. The controller can determine that the requests are to read or write data for the host (I/O) and appropriately handle the requests, which includes reading and writing data to the HMB as part of a read/write buffer (write data to memory or read data from memory) (102) as opposed to reading/writing to the SAT or iSAT (rather than for the table operations) [Col 7: line 58 – Col 8: line 9] [see Figs. 10A/10B] [Col 16: lines 49-67]. The memory device is part of the NVMe specification and the HMB is a highlighted feature of the NVMe protocol [Col 4: lines 33-43]).
Although Gunda teaches to allocate HMB space as a host read/write buffer, Gunda doesn’t explicitly disclose, but Pereira teaches that to use the HMB space as a read buffer - to store read data there for the host to access as part of a host read request (read I/O) (by teaching that part of the HMB (116) may be allocated as a read destination space (118) [Fig. 1A]. The read destination space (118) is reserved in the HMB for storing data read from the flash memory (126) as part of a read request [0027] [0042] [0055]. The data in the read destination space (118) may be error corrected in the read destination space (118) [0051] [0062-0063]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the allocation of host read/write buffer space in the HMB as taught by Gunda to include storing the read data there in the HMB for the host application to access as part of a read request as taught by Pereira.
One of ordinary skill in the art would have been motivated to make this modification because it reduces latency, power consumption, and cost of the storage device as taught by Pereira in [0065-0066].
Although Gunda teaches to allocate HMB space as a host read/write buffer, Gunda doesn’t explicitly disclose, but Jang teaches that to use the HMB space as a write buffer - to store write commands and data there (write I/O) from the host before they are processed during a later idle period (by teaching that the HMB may be used to queue/cache (buffer) write requests when there is a mixed read/write I/O pattern so that read requests may be prioritized. Later, when the device is idle, the write requests may be flushed/processed and stored to non-volatile memory in the storage device [0027-0029] [0032]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the allocation of host read/write buffer space in the HMB as taught by Gunda to include storing the write commands and data there in the HMB for the storage device to flush/process at a later time when the device is otherwise idle as taught by Jang.
One of ordinary skill in the art would have been motivated to make this modification because it may boost performance by up to 30% as taught by Jang in [0030].
Gunda in view of Pereira in further view of Jang do not explicitly disclose, but Hahn teaches, translate the first (and second) request into two address ranges, a logical block address (LBA) range (which is a single address range of the memory) and an error code address range (by teaching that data stored in the HMB includes both the data bits (131) and the parity bits (133). In this way, data read from the HMB or stored within the HMB is divided into two address ranges, one associated with the user data (data bits) (i.e. associated with the LBA of the read/write request [0055]) (LBA range, single address range of the memory) and the other associated with the parity bits (133) (error code range) [Fig. 1]) either: calculate error code write data for a write request; write IO write data to the memory; and write the calculated CRC write data to the translated CRC address range for the write request; and write data to the single address range (by teaching that when data is written (and write data to the single address range) (134) into the HMB, the data may have a new error code calculated (calculate the error code) and stored by the controller as the parity bits (133) along with the user write data (131) (write IO write data to the memory) in the HMB [0030-0032] [0036] [Fig. 1]); or read an error code stored at the translated CRC address range and IO read data stored at the translated LBA range for a read request, and compare the CRC read data to calculated CRC data, wherein the calculated CRC data is calculated from the IO read data (by teaching that when data is read from the HMB, the data bits (131) may be read and the 1st parity bits (133), then the first parity bits (133) may be compared with 2nd parity bits (139) (calculated CRC)); and determine whether to provide the IO read for the read request based on whether the CRC read data is equal to the calculated CRC data (by disclosing that when data is read from the HMB, if 2nd parity bits (139) do not match the 1st parity bits (133), the data read from the HMB is not used in the operation, but if the bits match, the data is validated and used [0038-0039] [0041]. Hahn teaches that any error correction code may be used, which includes those that correct or detect errors in data [0028).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read and write data stored in the HMB for host read and write requests as taught by Gunda in view of Pereira in further view of Jang to include being stored with a calculated parity code and have the parity code read and checked as part of a read operation from the HMB for the data so that if there is an uncorrectable error in the data the data is not used, and only validated data that has matching parity codes are read from the HMB and provided in response to the operation as taught by Hahn.
One of ordinary skill in the art would have been motivated to make this modification because it allows the controller to determine if the data read from the HMB has been corrupted or overwritten during the time the data was stored in the HMB as taught by Hahn in [0036].
Hahn does not explicitly disclose that the ECC code is a CRC code, but Xu teaches that an example of an error correcting code may be a CRC code (by teaching that CRC codes may be used to protect data in an HMB. When the read and calculated CRC codes do not match, the data that was read may be discarded [0045] [0053] [0071]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the parity bits as taught by Hahn, which may be any sort of error detecting or correcting codes as taught by Hahn [Hahn, 0028] with the CRC bits, which are also parity bits, as taught by Xu. One of ordinary skill in the art would have been motivated to make this modification because it would have only required the combination of known elements according to known methods to yield predictable results. For example, Hahn teaches parity bits, but does not restrict the parity bits to any particular type of error correction or detection code. Then, Xu teaches that a type of error detection code may be CRC. Both Hahn and Xu use the codes to determine whether an error exists in a HMB. Accordingly, one of ordinary skill in the art could have combined the use of the parity bits as taught by Hahn by implementing the particular CRC code scheme as taught by Xu according to known methods and the results would have been predictable. Furthermore, in combination, each element would continue to perform the same function that it did separately. Accordingly, the claim would have been obvious to one of ordinary skill in the art.
Gunda in view of Pereira in further view of Jang in further view of Hahn in further view of Xu do not explicitly disclose, but Schuette teaches, that the first request may be for gaming/streaming operations and determining that the first request is for IO operations rather than for the gaming/streaming operations and determining that the second request is for gaming or streaming operations such that the data written (to the single address range as taught by Hahn above does not include nonvolatile memory express (NVMe) protection information) (by teaching that a memory controller can determine if a request is for general purpose computing (IO) or for gaming operations [Fig. 1], in which case if the request is for gaming, the ECC is turned off (protection information – which is NVMe protection information as it is used in an NVMe memory device as taught in combination with Gunda), whereas if the request is for general purpose computing (IO), the ECC will be turned on [Fig. 1] [0017-0019]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the access to the HBM with two address ranges, one to the user data and one to CRC data in response to read and write requests as taught by Gunda in view of Pereira in further view of Jang in further view of Hahn in further view of Xu to include determining whether the request is from a gaming application so that error correction or detection may be turned off, such that only the data would be written (to a user data address range as taught by Hahn) without protection information (ECC or CRC) (i.e., no data would be written to an ECC or CRC address range as taught by Hahn in further view of Xu), or from regular IO so that error correction or detection may remain enabled (such that error correction or detection data (ECC or CRC) would be written to an error code address range alongside the user data written to the user data address range of the memory as taught by Hahn in further view of Xu) as taught by Schuette.
One of ordinary skill in the art would have been motivated to make this modification because for general purpose computing, error correction or detection is absolutely mandatory, but for gaming, it causes a high performance cost and is not necessary so it may be avoided as taught by Schuette in [0006-0008].
Regarding claim 2:
The data storage device of claim 1 is made obvious by Gunda in view of Pereira in further view of Jang in further view of Hahn in further view of Xu in further view of Schuette (Gunda-Pereira-Jang-Hahn-Xu-Schuette).
Gunda teaches that the storage device (102) that the host writes and reads data to/from is non-volatile flash memory [Col 6: lines 39-67]). Accordingly, storing the data in the HMB for host reads and writes to the storage device as taught by Gunda in view of Pereira in further view of Jang (as seen in the rejection for claim 1) include storing and managing data units in the HMB for non-volatile flash memory (flash management units). Therefore, the CRC protection data added to the data stored in the HMB for host reads and writes to the non-volatile flash memory as taught by Gunda-Pereira-Jang-Hahn-Xu-Schuette (as seen in the rejection for claim 1) may be interpreted as CRC protection data for a flash management unit (wherein the CRC is a flash management unit (FMU) CRC range).
Regarding claim 3:
The data storage device of claim 1 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda further discloses, wherein the memory is dynamic random access memory (DRAM) (by teaching that the HMB is made up of DRAM [Col 4: lines 19-33] [Col 6: lines 1-21].
Regarding claim 5:
The data storage device of claim 1 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda further discloses, wherein the memory is host memory buffer (HMB) (by teaching the host memory buffer (770) of the host memory (103) [Fig. 7]).
Regarding claim 6:
The data storage device of claim 1 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda further discloses, wherein the input/output operations comprise user data for write cache, user data for XOR recovery, or user data for read look ahead (that the I/O operations for the HMB may include I/O operations for data used in XOR recovery (1024), and data for a read and write buffer [Col 20: lines 38-42] [Col 16: line 49 – Col 17: line 2] [Col 21: lines 8-67] [Fig. 8] [Fig. 10A]).
Regarding claim 10:
The data storage device of claim 1 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda-Pereira-Jang-Hahn-Xu-Schuette teaches, wherein the controller is configured to: read the data from memory for a read request; and provide the data if the calculated CRC range equals the read CRC range (through the analysis performed for claim 1).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Gunda-Pereira-Jang-Hahn-Xu-Schuette in further view of US Patent No. US 6,513,094 B1 (Magro).
Regarding claim 4:
The data storage device of claim 3 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda further discloses that the host DRAM is partly used as a HMB may be accessed with DMA (by disclosing that a portion of the host memory (103), such as DRAM, is used for the HMB (770) [Col 13: lines 10-15]. Furthermore, the HMB may be accessed with DMA logic (753) of the storage controller (123) [Col 15: line 61 – col 16: line 2])
Gunda does not explicitly disclose, but Magro teaches, wherein the DRAM is coupled to a DRAM controller that comprises an arbiter, cache, and direct memory access (DMA) (by teaching that a host microprocessor (M) that controls SDRAM (100) (i.e. the host microprocessor is a DRAM controller) includes a PCI bridge to access peripherals (like NVM storage devices), includes arbiter (26), includes DRAM controller (20) further including a DRAM arbiter (21) as well as a write buffer (28) and read ahead buffer (30) (cache), and includes GPDMA controller (DMA) [Fig. 2]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the host with CPU processor and memory (DRAM) as taught by Gunda to include the microprocessor features for interfacing with the memory (DRAM) and a ROM on the same bus as taught by Magro including the read ahead buffer and write buffer (cache), the DRAM arbiter (21) and arbiter (26) (arbiter), and the GPDMA controller (22).
One of ordinary skill in the art would have been motivated to make this modification because the arbiters allow multiple concurrent transactions to occur without a collision on a single bus without the expense of multiple buses, but while preserving data persistence on the ROM as well as the speed of DRAM as taught by Magro in [Col 1: lines 13-35] [Col 6: line 24- Col 7: line 11]. Furthermore, the read-ahead and write buffer techniques optimize DRAM system performance [Col 3: lines 50-55]. Finally, the DMA allows for DMA transactions between bus peripherals and DRAM, which allows for direct data transfer between the peripherals and DRAM that doesn’t involve the CPU and waste CPU cycles to enhance system performance [Col 4: lines 9-23].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gunda-Pereira-Jang-Hahn-Xu-Schuette in further view of US Patent Application Publication No. US 2020/0117814 A1 (Ito).
Regarding claim 7:
The data storage device of claim 1 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda-Pereira-Jang-Hahn-Xu-Schuette teaches wherein the controller generates CRC parity bits.
Xu does not explicitly disclose, but Ito teaches does not generate error correction code (ECC) (by teaching that CRC is an alternative to be used instead of ECC [0043]). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of ECC parity bits, such as taught by Hahn, to instead include CRC parity bits and not ECC as taught by Ito because it would have only required the simple substation of one known element for another to yield predictable results. For example, Hahn teaches using ECC parity bits, but does not teach using CRC parity bits, however, Ito teaches that you can use CRC schemes instead of ECC/EDC. One of ordinary skill in the art could have substituted the ECC for the CRC taught by Ito and the results would have been predictable. Furthermore, Ito recognizes ECC and CRC as alternatives and recognizes that one may be substituted for the other. Accordingly, the substitution would have been obvious to one of ordinary skill in the art.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Gunda-Pereira-Jang-Hahn-Xu-Schuette in further view of US Patent No. US 6,901,551 B1 (Corrigan).
Regarding claim 8:
The data storage device of claim 1 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette.
Gunda-Pereira-Jang-Hahn-Xu-Schuette do not explicitly disclose, but Corrigan teaches, wherein the controller is configured to determine whether the data includes metadata and protection information (by teaching that different address ranges are used to communicate whether the CRC data should be generated, whether to check the CRC error data (metadata), or whether it is a normal access that does not include the use of CRC [Fig. 2].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the creation of CRC data for data stored in a memory to be dependent on determining the memory address range that is accessed to determine whether it already exists and needs to be read (including CRC error data (metadata)) or whether it does not exist and needs to be calculated and written as taught by Corrigan.
One of ordinary skill in the art would have been motivated to make this modification because it allows the CRC to be generated transparently on-the-fly without software overhead as taught by Corrigan in [Col 1: line 62 – Col 2: line 9].
Regarding claim 9:
The data storage device of claim 8 is made obvious by Gunda-Pereira-Jang-Hahn-Xu-Schuette in further view of Corrigan.
Gunda-Pereira-Jang-Hahn-Xu-Schuette do not explicitly disclose, but Corrigan teaches wherein the controller is configured to generate and inject protection information to the data when not included by a host (by teaching that when the address range indicates that the data should be protected (and the CRC is not provided by the host), the CRC data (protection information) should be generated (504 -> Yes) and stored with the write data [Fig. 5]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the creation of CRC data for data stored in a memory to be dependent on determining the memory address range that is accessed to determine whether it already exists and needs to be read (including CRC error data (metadata)) or whether it does not exist and needs to be calculated and written as taught by Corrigan.
One of ordinary skill in the art would have been motivated to make this modification because it allows the CRC to be generated transparently on-the-fly without software overhead as taught by Corrigan in [Col 1: line 62 – Col 2: line 9].
Response to Amendments/Arguments
In response to the amendments to the claims, new claim objections have been made as seen in the corresponding claim objection section above.
In response to the amendments to the claims, the previous 35 USC §112(b) rejections have been withdrawn, however a new 35 USC §112(b) rejection has been made to claims 8-10 as seen in the corresponding rejection section above.
In response to the amendments to the claims, the 35 USC §112(a) rejection has been withdrawn.
In response to the amendments to the claims, a new 35 USC §103 rejection based on the combination of references, including Schutte, has been made as seen above. Applicant does not provide any particular arguments regarding how Schuette’s teachings to forgo error correction for gaming/streaming operations does not make obvious the newly amended limitations in combination with the other cited references. Accordingly, Applicant’s argument is not persuasive and the claims are rejected under 35 USC §103 as seen in the corresponding rejection section above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2017/0300246 A1 (Michaeli) – teaches to use CRC data to protect and correct an L2P map stored in a HMB [Fig. 3] [0053-0054] [0058-0059].
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139