DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krasulick (US 2016/0111407) in view of Kim et al. (KR20160136103A, art cited by applicant and English machine translation is used herewith).
Regarding claim 1, Krasulick teaches a large-area III-V semiconductor layer transferring method comprising: forming III-V semiconductor dies (III-V die) on a lower substrate; forming dielectric patterns on the III-V semiconductor dies and the lower (SOI substrate) substrate exposed between the III-V semiconductor dies; and bonding an upper substrate (base layer) onto the III-V semiconductor layer (figs. 3A-3E). See also, [0044]-[0055]).
Krasulick fails to teach forming a lower III-V semiconductor layer on the dielectric patterns and the III-V semiconductor dies; forming a sacrificial layer on the lower III-V semiconductor layer; forming an upper III-V semiconductor layer on the sacrificial layer; bonding an upper substrate onto the III-V semiconductor layer; and removing the sacrificial layer.
However, Kim teaches a large-area III-V semiconductor layer transferring method comprising: forming a lower III-V semiconductor layer (135) on the dielectric patterns and the III-V semiconductor dies; forming a sacrificial layer (155) on the lower III-V semiconductor layer; forming an upper III-V semiconductor layer (165) on the sacrificial layer; bonding an upper substrate onto the III-V semiconductor layer; and removing the sacrificial layer (figs. 2a-2c; [0030]-[0034]).
In view of Kim’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Krasulick by incorporating the teaching as taught by Kim in order to arrive at the claimed invention.
Regarding claim 2, Krasulick as modified by Kim all subject matter claims as applied above. Both Krasulick and Kim further teach wherein each of the III-V semiconductor dies comprises InP and GaAs (Krasulick: [0072], [0075] and [0078]. Kim: [0003]).
Regarding claim 3, Krasulick as modified by Kim all subject matter claims as applied above. Both Krasulick and Kim further teach wherein each of the dielectric patterns comprises silicon oxide formed by an epitaxial lateral over growth (ELOG) method (Krasulick: [0075]. Kim: [0031], [0033] and [0034]).
Regarding claim 4, Krasulick as modified by Kim all subject matter claims as applied above. Krasulick further teaches wherein each of the dielectric patterns has a T-shape (fig. 1).
Regarding claim 5, Krasulick as modified by Kim all subject matter claims as applied above. Krasulick further teaches wherein each of the III-V semiconductor dies has a comb shape (fig. 3C).
Regarding claim 6, Krasulick as modified by Kim all subject matter claims as applied above. Krasulick further teaches wherein the lower substrate comprises silicon wafer ([0039] and [0041]).
Regarding claim 7, Krasulick as modified by Kim all subject matter claims as applied above. Krasulick further teaches wherein the upper substrate comprises a silicon on insulator (SOI) substrate ([0036] and [0039]).
Regarding claim 9, Krasulick as modified by Kim all subject matter claims as applied above. Both Krasulick and Kim further teach wherein the lower III-V semiconductor layer comprises InP or GaAs formed by an epitaxial lateral over growth (ELOG) method (Krasulick: 0072], [0075]. Kim: [0003], [0031], [0033] and [0034]).
Regarding claim 10, Krasulick as modified by Kim all subject matter claims as applied above. Wherein the upper III-V semiconductor layer comprises InP or GaAs on a large-area lower III-V/Si substrate (Krasulick: [0075]. Kim: [0003]).
Regarding to claims 11 and 12, the claim recites similar subject matter as in claim 1 and therefore, same rationale is applied as for claim 1 above.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krasulick as modified by Kim as applied to claim 1 above, and further in view of Ju (KR101112118B1, art cited by applicant and English machine translation is used herewith).
Regarding claim 8, Krasulick as modified by Kim teaches all subject matter claimed as applied above except for each of the dielectric patterns has a thickness of about 1 µm or less.
However, Ju teaches method for manufacturing III-nitrite substrate that the intermediate layer is form on the substrate having a thickness of about 1 µm or less ([0049]-[0052]).
In view of Ju’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Krasulick and Kim by incorporating the teaching as taught by Ju since it is just a mater of design option for selecting the thickness of the dielectric patterns.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
References: Bower et al. (US 2019/0088690); Cheng et al. (US 10,037,989); Liou et al. (US 2017/0005181) and Chen et al. (US 2014/0220482) are cited because they are related to method for manufacturing semiconductor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuyen Kim Vo whose telephone number is (571)270-1657. The examiner can normally be reached Mon-Thurs: 8AM-6:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Paik can be reached at 571-272-2404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUYEN K VO/ Primary Examiner, Art Unit 2876
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