DETAILED ACTION
This action is responsive to communication filed 02/02/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 8 in the reply filed on 02/02/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden found in the remaining claims. This is not found persuasive because applicant has not given a reason as to why there is no serious burden as examiner stated in the action dated 12/29/2026 in paragraph 6 where mutually exclusive characteristics such as those described in paragraph 4, such as the shape of the vias and the number and arrangement of channels and gates, would require performing many different searches.
The requirement is still deemed proper and is therefore made FINAL.
Claims 8-10 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/02/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the pixel circuit". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination “the pixel circuit” will instead be interpreted as “a pixel circuit”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5-7, 12-14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20220139966 A1).
Regarding claim 1 Kim et al. (see, e.g., FIG. 5) discloses an array substrate, comprising:
a semiconductor pattern (130),
a first gate (155a),
a second gate (155e and 155f) and
a first metal part (171 and 172),
wherein the semiconductor pattern comprises a first channel (131a) overlapping with the first gate,
a second channel (131e and 131f) overlapping with the second gate,
and a first connection part (136a, 136f, 137a, and 137e) connecting the first channel with the second channel;
and the first metal part overlaps with the first connection part and is electrically connected to the first connection part (electrically connected via 64, 136e and 131e).
Regarding claim 3, Kim et al. (see, e.g., FIG. 5) discloses the array substrate according to claim 1, wherein:
a size of the first metal part in a first direction (DR2) is larger than a size of the first metal part in a second direction (DR1),
the first direction intersects with an extension direction (see paragraph [0093] where both DR1 or DR2 are extension directions, for the purposes of this claim DR1 is the extension direction) of the semiconductor pattern,
and the second direction is the same as the extension direction of the semiconductor pattern,
or a size of the first metal part in a first direction is smaller than or equal to a size of the first connection part in the first direction,
and the first direction intersects with an extension direction of the semiconductor pattern.
Regarding claim 5, Kim et al. (see, e.g., Annotated FIG. 5 below) discloses the array substrate according to claim 1, wherein:
the first metal part comprises a first sub-metal part (172) and a second sub-metal part (171) which are spaced apart from each other;
in an extension direction (DR1) of the semiconductor pattern,
a distance between the first sub-metal part and the first channel (see annotated Fig. 5 below: “first distance”) is smaller than a distance between the first sub-metal part and the second channel (see annotated Fig. 5 below: “fourth distance”),
and a distance between the second sub-metal part and the second channel (see annotated Fig. 5 below: “second distance”) is smaller than a distance between the second sub-metal part and the first channel (see annotated Fig. 5 below: “third distance”).
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Regarding claim 6, Kim et al. (see, e.g., FIG. 5) discloses the array substrate according to claim 1, wherein:
the first metal part is electrically connected to the first connection part through a first via hole (64).
Regarding claim 7, Kim et al. (see, e.g., FIG. 5) discloses the array substrate according to claim 6, wherein:
a plurality of first via holes are provided (64, 66, and 69) and are arranged in a first direction (DR2),
and the first direction intersects with an extension direction (DR1) of the semiconductor pattern.
Regarding claim 12, Kim et al. (see, e.g., FIGS. 1 and 4) discloses the array substrate according to claim 1, further comprising:
a pixel circuit (Fig. 1: CP) comprising a driving transistor (Fig. 4: T1) and a light emitting control transistor (Fig. 4: T5 and T6),
wherein the driving transistor comprises the first gate and the first channel,
and the light emitting control transistor comprises the second gate and the second channel.
Regarding claim 13, Kim et al. (see, e.g., FIG. 5) discloses the array substrate according to claim 12, wherein:
the semiconductor pattern further comprises an electrode connection part (137f) which is located at one side of the second channel away from the first connection part in an extension direction of the semiconductor pattern;
the array substrate further comprises an electrode metal part (164) which overlaps with the electrode connection part and is electrically connected to the electrode connection part;
and the electrode metal part is electrically connected to a signal trace or an electrode of a light emitting device (191).
Regarding claim 14, Kim et al. (see, e.g., FIG. 5) discloses the array substrate according to claim 13, wherein:
the first metal part is electrically connected to the first connection part through a first via hole (64),
and the electrode metal part is electrically connected to the electrode connection part through a third via hole (65).
Regarding claim 16, Kim et al. (see, e.g., FIG. 6 (Note: Figure 6 provides a cross section containing only a portion of the elements of a given layer and is being used to identify the relative locations of each layer. Examiner will identify in the following claim what elements visible in FIG. 6 are in the same layer as elements required by claim 16)) discloses the array substrate according to claim 1, further comprising:
a substrate (110);
and a driving device layer (semiconductor layer 130 defined in paragraphs [0103] and [0104], first conductive layer defined in paragraphs [0100], second conductive layer defined in paragraph [0101], and third conductive layer defined in paragraph [0101]) on the substrate,
wherein the driving device layer comprises a semiconductor layer (semiconductor layer 130 defined in paragraph [0104] to include 131a-131g, of which 131a is visible in Fig. 6),
a first metal layer (first conductive layer defined in paragraph [0100] to include 151-154 and 155a, of which 155a is visible in Fig. 6),
a capacitor metal layer (second conductive layer defined in paragraph [0101] to include 127, 128, 156, and 157, of which 157 is visible in Fig. 6)
and a second metal layer (third conductive layer defined in paragraph [0101] to include 161, 164, 167, 171, and 172, of which 161 is visible in Fig. 6)
which are stacked (paragraph [0101]: “The second conductive layers (127, 128, 156, and 157) may be disposed on a layer disposed on the first conductive layers” and “The third conductive layers (161, 164, 167, 171, and 172) may be disposed on a layer provided on the second conductive layers”),
the semiconductor layer is located between the substrate and the first metal layer (see Fig. 6: 131a which is part of the semiconductor layer 130 is between substrate 110 and 155a which is part of the first conductive layer),
the capacitor metal layer is located at one side of the first metal layer away from the semiconductor layer (see Fig. 6: 157 which is part of the second conductive layer on opposite side of 155a as 131a),
and the second metal layer is located at one side of the capacitor metal layer away from the first metal layer (see Fig. 6: 161 which is part of the third conductive layer on opposite side of 157 as 155a),
wherein the semiconductor pattern is located in the semiconductor layer;
the first gate and the second gate are located in the first metal layer;
one of electrode plates (157) of a capacitor (Fig. 4: Cst) of a pixel circuit (Fig. 4: PX) is located in the capacitor metal layer;
and the first metal part is located in the second metal layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220139966 A1) as applied to claim 1 above.
Regarding claim 2, Kim et al. fails to explicitly teach the array substrate according to claim 1, wherein:
a conductivity of the first metal part is greater than a conductivity of the first connection part,
and/or a potential of the first metal part is floating.
However, Kim et al. does teach that the first metal part 172 is a driving voltage line (paragraph [0078]) which are generally highly conductive to reduce voltage drop across the line, and that the connection part should have reduced width (see Fig. 2: W2), which would reduce conductivity, in order to reduce parasitic capacitance without affecting the channel negatively (paragraphs [0055]-[0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al. in order to decrease voltage drop in the voltage line and reduce parasitic capacitance in the system (paragraphs [0055]-[0057]).
Regarding claim 4, Kim et al. (see, e.g., FIG. 5) discloses the array substrate according to claim 1, wherein:
the first metal part is spaced from the first gate by an interval d1 in an extension direction of the semiconductor pattern,
or the first metal part is spaced from the second gate by the interval d1 in the extension direction of the semiconductor pattern (172 is space apart in direction DR1 from either 155e or 155f which are defined by the intersection of 153 and either T5 or T6 respectively, as can be seen in FIG. 8),
wherein 1um<=d1<=5um.
While, Kim et al. fails to define the proportions of their device they acknowledge that a goal of the field is to reduce thickness and weight of the device (paragraph [0003]), which reducing the distance of internal pieces would accomplish, and where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984) (see, e.g., MPEP 2144.04(IV)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al. as a simple change in size that would yield predictable results.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220139966 A1) as applied to claim 1 above, and further in view of Kim et al. (US 20220013670 A1) hereinafter referred to as “Kim 2”.
Regarding claim 11, Kim et al. fails to expressly teach the array substrate according to claim 1, wherein:
a width of the first channel is greater than or equal to 10um,
and/or a width of the second channel is greater than or equal to 10um.
Kim 2 (see, e.g., FIG. 1A) discloses a thin film transistor (100A) for use in an OLED display, wherein the first channel (104A) has a width greater than or equal to 10um (paragraph [0025]: “40 um”) in order to improve the mobility of the transistor (paragraph [0025]) which would reduce image distortion (paragraph [0003]). Additionally, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (see also MPEP 2144.05(I)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al. with Kim 2 in order to reduce image distortion in the display (paragraph [0003]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220139966 A1) as applied to claim 12 above, and further in view of Rankov et al. (US 9755010 B2).
Regarding claim 15 Kim et al. (see, e.g., FIG. 4) discloses the array substrate according to claim 12, wherein:
the pixel circuit further comprises a first transistor (Any from among T2, T3, T4, or T7),
a width-to-length ratio of a channel of the driving transistor is greater than a width-to-length ratio of a channel of the first transistor,
and/or a width-to-length ratio of a channel of the light emitting control transistor is greater than a width-to-length ratio of a channel of the first transistor.
Rankov et al. discloses that a channel of a driving transistor would have a greater width to length ratio compared to switching transistors in order to allow operation at lower voltages (column 2, lines 28-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al. with Rankov et al. in order to allow operation of the driving transistor at lower voltages (column 2, lines 28-30).
Allowable Subject Matter
Claims 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN D BANKLER whose telephone number is (571)272-0883. The examiner can normally be reached Monday through Friday 9:00-5:00.
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/AIDAN D BANKLER/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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