DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign applications KR10-2023-0038972 filed on 03/24/2023 and KR10-2023-0046197 filed on 04/07/2023. The foreign applications are not in English. The certified copy of the foreign priority applications KR10-2023-0038972 and KR10-2023-0046197 have been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
Applicant has not yet complied with one or more conditions to actually be entitled to benefit of an earlier filing date under 35 U.S.C. 119(a)-(d).
To be entitled to the filing date of the foreign priority applications KR10-2023-0038972 and KR10-2023-0046197 that are not in English, English translations of each of the non-English language foreign applications KR10-2023-0038972 and KR10-2023-0046197 and a statement that the corresponding translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application(s) must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Response to Amendment
Applicant’s amendment dated 03/20/2026, in which claims 1, 9, 12-13, 16, were amended, claims 10-11 were cancelled, has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of “the landing pad does not directly contact the insulating spacer” of claim 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-8, 16, 19-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Park et al. (US Pub. 20230005924), hereafter Park924
Regarding claim 1, Park924 discloses in Fig. 2, Fig. 8, Fig. 12, Fig. 18 an integrated circuit device comprising:
a substrate [101] having an active area [ACT][paragraph [0018]];
a plurality of bit line structures [BL] on the substrate [101], wherein a bit line structure [BL] of the plurality of bit line structures [BL] includes an insulating spacer [121, 122, 125] on a sidewall thereof [paragraph [0027]];
a buried contact [BC] between the plurality of bit line structures [BL], and electrically connected to the active area [ACT][paragraph [0026]];
an insulation capping pattern [137] on the bit line structure [BL] extending higher than the insulating spacer [121, 122, 125] from the substrate [101] such that a side surface of the insulation capping pattern [137] is exposed from the insulating spacer [121, 122, 125] [Fig. 8, paragraph [0023], [0050]]; and
a landing pad [LP] electrically connected to the buried contact [BC], the landing pad [LP] arranged to vertically overlap the bit line structure [BL] on the insulation capping pattern [137], wherein an uppermost surface of the landing pad [LP] is higher than an uppermost surface of the insulation capping pattern [137] relative to the substrate [101][paragraph [0028]].
Regarding claims 6-7, Park924 discloses in Fig. 12, Fig. 18, paragraph [0034]
wherein the insulating spacer [121, 122, 125] extends on a side surface of the insulation capping pattern [137], and further comprising:
a node separation pattern [BP] contacting the side surface of the insulation capping pattern [137] and contacting an upper surface of the insulating spacer [121, 122, 125] on the side surface of the insulation capping pattern [137];
wherein the node separation pattern [BP] contacts the landing pad [LP].
Regarding claim 8, Park924 discloses the insulation capping pattern but does not disclose the insulation capping pattern comprises an epitaxial layer. However, “epitaxial layer” directs to a product-by-process limitation. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Furthermore, "[b]ecause validity is determined based on the requirements of patentability, a patent is invalid if a product made by the process recited in a product-by-process claim is anticipated by or obvious from prior art products, even if those prior art products are made by different processes." Amgen Inc. v. F. Hoffman-La Roche Ltd., 580 F.3d 1340, 1370 n 14, 92 USPQ2d 1289, 1312, n 14 (Fed. Cir. 2009). (MPEP 2113). In this case, Park924 discloses the insulation capping pattern thus it meets the claim.
Regarding claim 16, Park924 discloses in Fig. 2, Fig. 8, Fig. 12, Fig. 18 an integrated circuit device comprising:
a substrate [101] having an active area [ACT] defined by an element separation area [102][paragraph [0018]];
a pair of bit line structures [BL] on the substrate [101], and comprising an insulating spacer [121, 122, 125] on a sidewall of a bit line structure [BL] of the pair of bit line structures [BL][paragraph [0027]];
a buried contact [BC] between the pair of bit line structures [BL], and electrically connected to the active area [ACT][paragraph [0026]];
an insulation capping pattern [137] on the bit line structure [BL] extending higher than the insulating spacer [121, 122, 125] from the substrate [101] such that a side surface of the insulation capping pattern [137] is exposed from the insulating spacer [121, 122, 125][Fig. 8, paragraph [0023], [0050]];
a landing pad [LP] electrically connected to the buried contact [BC], the landing pad [LP] arranged to vertically overlap the bit line structure [BL] on the insulation capping pattern [137][paragraph [0028]]; and
a capacitor structure [CAP] on the landing pad [LP], and including a capacitor lower electrode [BE] electrically connected to the landing pad [LP][paragraph [0030]-[0032]],
wherein an uppermost surface of the landing pad [LP] is higher than an uppermost surface of the insulation capping pattern [137] relative to the substrate [101][paragraph [0028]].
Regarding claims 19-20, Park924 discloses in Fig. 2, Fig. 8, Fig. 12, Fig. 18, paragraph [0034]
wherein the insulating spacer [121, 122, 125] extends on a side surface of the insulation capping pattern [137], and further comprising:
a node separation pattern [BP] contacting the side surface of the insulation capping pattern [137] and contacting an upper surface of the insulating spacer [121, 122, 125] arranged on the side surface of the insulation capping pattern [121, 122, 125],
wherein the node separation pattern [BP] contacts the landing pad [LP];
wherein the upper surface of the insulating spacer [121, 122, 125], which does not vertically overlap the landing pad [LP], is surrounded by the node separation pattern [BP].
Claims 1, 6-9, 15-16, 19-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Park et al. (US Pub. 20150214291), hereafter Park291.
Regarding claim 1, Park291 discloses in Fig. 1 an integrated circuit device comprising:
a substrate [110] having an active area [116][paragraph [0029]];
a plurality of bit line structures [140] on the substrate [110], wherein a bit line structure [140] of the plurality of bit line structures [140] includes an insulating spacer [150] on a sidewall thereof [paragraph [0032]];
a buried contact [170] between the plurality of bit line structures [140], and electrically connected to the active area [116][paragraph [0037]];
an insulation capping pattern [144 and 160] on the bit line structure [140] extending higher than the insulating spacer [150] from the substrate such that a side surface of the insulation capping pattern [144 and 160] is exposed from the insulating spacer [150][paragraph [0032]]; and
a landing pad [172] electrically connected to the buried contact [170], the landing pad [172] arranged to vertically overlap the bit line structure [140] on the insulation capping pattern [144 and 160], wherein an uppermost surface of the landing pad [172] is higher than an uppermost surface of the insulation capping pattern [144 and 160] relative to the substrate [110][paragraph [0038]].
Regarding claims 6-7, Park291 discloses in Fig. 1, paragraph [0035]
wherein the insulating spacer [150] extends on a side surface of the insulation capping pattern [144 and 160], and further comprising: a node separation pattern [162] contacting the side surface of the insulation capping pattern [144 and 160] and contacting an upper surface of the insulating spacer [150] on the side surface of the insulation capping pattern [144 and 160];
wherein the node separation pattern [162] contacts the landing pad [172].
Regarding claim 8, Park291 discloses the insulation capping pattern but does not disclose the insulation capping pattern comprises an epitaxial layer. However, “epitaxial layer” directs to a product-by-process limitation. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Furthermore, "[b]ecause validity is determined based on the requirements of patentability, a patent is invalid if a product made by the process recited in a product-by-process claim is anticipated by or obvious from prior art products, even if those prior art products are made by different processes." Amgen Inc. v. F. Hoffman-La Roche Ltd., 580 F.3d 1340, 1370 n 14, 92 USPQ2d 1289, 1312, n 14 (Fed. Cir. 2009). (MPEP 2113). In this case, Park291 discloses the insulation capping pattern thus it meets the claim.
Regarding claim 9, Park291 discloses in Fig. 1, Fig. 3, Fig. 4E an integrated circuit device comprising:
a substrate [110] including a cell area and a peripheral area [paragraph [0059]-[0060]];
a plurality of bit line structures [140] on the cell area, wherein a bit line structure [140] of the plurality of bit line structures [140] includes an insulating spacer [150] on a sidewall thereof [paragraph [0032], [0059]];
a buried contact [170] between the plurality of bit line structures [140][paragraph [0037]];
an insulation capping pattern [144 and 160] on the bit line structure [140] extending higher than the insulating spacer [150] from the substrate such that a side surface of the insulation capping pattern [144 and 160] is exposed from the insulating spacer [150][paragraph [0032]]; and
a landing pad [172] electrically connected to the buried contact [170], the landing pad [172] arranged to vertically overlap the bit line structure [140] on the insulation capping pattern [144 and 160][paragraph [0038]].
Regarding claim 15, Park291 discloses Fig. 1, Fig. 3, paragraph [0029], [0037], [0059]
wherein the cell area comprises an active area [116] defined by an element separation area [114], and the buried contact [170] is electrically connected to the active area [116].
Regarding claim 16, Park291 discloses in Fig. 1 an integrated circuit device comprising:
a substrate [110] having an active area [116] defined by an element separation area [114][paragraph [0029]];
a pair of bit line structures [140] on the substrate [110], and comprising an insulating spacer [150] on a sidewall of a bit line structure of the pair of bit line structures [140][paragraph [0032]];
a buried contact [170] between the pair of bit line structures [140], and electrically connected to the active area [116][paragraph [0037]];
an insulation capping pattern [144 and 160] on the bit line structure [140] extending higher than the insulating spacer [150] from the substrate such that a side surface of the insulation capping pattern [144 and 160] is exposed from the insulating spacer [150][paragraph [0032]];
a landing pad [172] electrically connected to the buried contact [170], the landing pad [172] arranged to vertically overlap the bit line structure [140] on the insulation capping pattern [144 and 160][paragraph [0038]]; and
a capacitor structure on the landing pad [172], and including a capacitor lower electrode [180] electrically connected to the landing pad,
wherein an uppermost surface of the landing pad [172] is higher than an uppermost surface [160A] of the insulation capping pattern [144 and 160] relative to the substrate [110][paragraph [0038]-[0042]].
Regarding claims 19-20, Park291 discloses in Fig. 1, paragraph [0035]
wherein the insulating spacer [150] extends on a side surface of the insulation capping pattern [144 and 160], and further comprising:
a node separation pattern [162] contacting the side surface of the insulation capping pattern [144 and 160] and contacting an upper surface of the insulating spacer [150] on the side surface of the insulation capping pattern [144 and 160];
wherein the node separation pattern [162] contacts the landing pad [172];
wherein the upper surface of the insulating spacer [150], which does not vertically overlap the landing pad [172], is surrounded by the node separation pattern [162].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 20150214291), hereafter Park291 as applied to claim 1, claim 9 and claim 16 above.
Regarding claims 2, 12 and 17, Park291 discloses in Fig. 1
wherein the uppermost surface of the landing pad [172] is higher than the uppermost surface [160A] of the insulation capping pattern [144 and 160] by a distance, relative to the substrate.
Park291 fails to disclose
the distance is about 300Å to 1500Å.
However, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Park291 to include the distance is about 300Å to 1500Å; or to include the uppermost surface of the landing pad is higher than the uppermost surface of the insulation capping pattern by about 300Å to 1500Å, relative to the substrate. The ordinary artisan would have been motivated to modify Park291 in the manner set forth above for at least the purpose of optimization and routine experimentation to provide sufficient thickness of the landing pad. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claims 3-5, 13, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 20150214291), hereafter Park291 as applied to claim 1, claim 9 and claim 17 above and further in view of Seo et al. (US Pub. 20110186923).
Regarding claim 3, Park291 discloses in Fig. 1, paragraph [0074], [0090]
wherein the insulation capping pattern [144 and 160] comprises a first layer [144] including silicon nitride, and a second layer [160].
Park291 further discloses the second layer including silicon oxide.
Park291 fails to disclose the second layer including tetra-ethyl-ortho- silicate (TEOS).
However, tetra-ethyl-ortho- silicate (TEOS) is a known silicon oxide and therefore it would have been obvious to select it based on it suitability for use as the silicon oxide material in the device of Park et al. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Seo et al. discloses in Fig. 10C, paragraph [0056]
the second layer [170] including tetra-ethyl-ortho- silicate (TEOS).
Seo et al. further discloses tetra-ethyl-ortho- silicate (TEOS) is a silicon oxide layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Seo et al. into the method of Park291 to include the second layer including tetra-ethyl-ortho- silicate (TEOS). The ordinary artisan would have been motivated to modify Park291 in the above manner for the purpose of providing suitable silicon oxide material including in the second layer [paragraph [0056] of Seo et al.].
Regarding claims 4-5, Park291 discloses in Fig. 1
wherein a thickness of the second layer [160] is substantially identical to a height difference between the uppermost surface of the landing pad [172] and the uppermost surface [160A] of the insulation capping pattern [144 and 160], along a direction perpendicular to the substrate [110];
wherein an interface between the first layer [144] and the second layer [160] is substantially planar in a direction in parallel with the substrate [110].
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Regarding claims 13 and 18, Park291 discloses in Fig. 1, paragraph [0074], [0090]
wherein the insulation capping pattern [144 and 160] comprises a first layer [144] including silicon nitride, and a second layer [160];
wherein a thickness of the second layer [160] is substantially identical to a height difference between an uppermost surface of the landing pad [172] and the uppermost surface [160A] of the insulation capping pattern [144 and 160], along a direction perpendicular to the substrate [110].
Park291 further discloses the second layer including silicon oxide.
Park291 fails to disclose the second layer including tetra-ethyl-ortho- silicate (TEOS).
However, tetra-ethyl-ortho- silicate (TEOS) is a known silicon oxide and therefore it would have been obvious to select it based on it suitability for use as the silicon oxide material in the device of Park291 Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Seo et al. discloses in Fig. 10C, paragraph [0056]
the second layer [170] including tetra-ethyl-ortho- silicate (TEOS).
Seo et al. further discloses tetra-ethyl-ortho- silicate (TEOS) is a silicon oxide layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Seo et al. into the method of Park291 to include the second layer including tetra-ethyl-ortho- silicate (TEOS). The ordinary artisan would have been motivated to modify Park291 in the above manner for the purpose of providing suitable silicon oxide material including in the second layer [paragraph [0056] of Seo et al.].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 20150214291), hereafter Park291 as applied to claim 9 above and further in view of Park et al. (US Pub. 20230005924), hereafter Park924.
Regarding claim 14, Park291 fails to disclose
wherein the landing pad does not directly contact the insulating spacer.
Park924 discloses in Fig. 2, paragraph [0028], [0052]
wherein the landing pad [LP] does not directly contact the insulating spacer [121, 123, 125].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Park924 into the method of Park291 to include wherein the landing pad does not directly contact the insulating spacer. The ordinary artisan would have been motivated to modify Park291 in the above manner for the purpose of forming a diffusion prevention pattern between landing pad and adjacent elements. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 1-9, 12-20 have been considered but are moot in view of the new ground of rejection.
In addition, Applicant's arguments filed 03/20/2026 have been fully considered but they are not persuasive.
Regarding Applicant’s statement that “The Examiner suggested that an alternative amendment specifying that the insulation capping layer extends higher than the insulating spacer such that a side surface of the insulating capping pattern is exposed from the insulating spacer would distinguish over the Kim reference. The Examiner also agreed that such the amendment would distinguish over the Park reference” is incorrected. The claimed language was not presented at the time of the interview. Therefore, no agreement with respect to the current amendment was reached. During the interview, Examiner agreed the insulation capping layer of the Kim reference does not extend higher than the insulating spacer but Examiner did not agree that such an amendment would distinguish over the Park reference without further distinguish the profile/shape of the insulation capping layer.
As stated in the rejection, Park does disclose the insulation capping layer [144 and 160] extends higher than the insulating spacer [150] such that a side surface [side surface of 160] of the insulating capping pattern [144 and 160] is exposed from the insulating spacer [150].
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Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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