DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/06/2026 has been entered.
Applicant's arguments filed on 12/15/2025 with respect to claims 1, 2, 4-6, 8-15 and 17-20 have been fully considered but are moot in view on newly cited reference.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 8-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by He et al. (US pub. # 2023/0342087), hereinafter, “He”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claim 8, He discloses a system, comprising: one or more processors (CPU 341 of fig. 2, as disclose in paragraphs 0054, 058 and 0070) coupled to memory (memory 342), the processor configured to: responsive to a process in a user space (see paragraph 0045, which discloses “the host is configured to generate or consume data, for example, may be an application server, a distributed file system server, or the like” and fig. 5, which discloses data from a server, host to a SQ, QP. The data came from the server, a user space. Note, the claim language doesn’t provide much detail in regards to a ‘user space’), set a first queue pair (QP) (QP1 of fig. 2) of a plurality of QPs (QP1 and QP2 in memory 342; see fig. 2 and paragraph 0054) responsive to a first process in a user space (see paragraphs 0070 and 0073), a first resource set of the first QP allocated from the memory in a kernel space (see paragraphs 0070 and 0076); set a second QP (QP2 of fig. 2) of the plurality of QPs responsive to a second process in the user space, a second resource set of the second QP allocated from the memory in the kernel space (see paragraph 0054, which discloses “during data writing, the application server 210 generates data by using the CPU 211 and stores the generated data in the memory 212, then writes the data into the memory 242 of the storage server 240 through the RNIC 213, and notifies, based on the SQ address of the SSD 244, the SSD 244 to migrate the data in the memory 242 to the SSD 244 for persistent storage. If another application server needs to write data to the storage server 240, a process is similar to that in the foregoing description, and details are not described herein again”); and set a pool of shared send queues (SSQs) (see paragraph 0054, which teaches multiples of SQs and associated QPs or any number of SQs, QPs) comprising at least one SSQ (SQ1 of memory 342 combined with SQ2 of memory 342. Note, the recited phrase ‘at least one’ is opened to one or more; in other words, the combination of SQ1 and SQ2 has at least one in it), the at least one SSQ being shared by the first QP and the second QP (see paragraph 0054, which discloses “Each application server is connected to the storage server, to form a QP. Therefore, the memory 242 of the storage server 240 has a plurality of QPs, for example, a QP1, a QP2, and a QP3, and each QP corresponds to a connection between the storage server 240 and one application server. ... The application server 210 is used as an example, to describe a specific binding process of the SQ and the QP…. In addition, the storage server 240 binds the SQs in the SSD 244 to the stored QPs one by one, for example, binds the QP1 connected to the application server 210 to an SQ1. Then, an address of the SQ1 is mapped, and a virtual address obtained through mapping is registered with the RNIC 243. The RNIC 243 sends the address of the SQ1 to the RNIC 213 through an RDMA connection, so that the RNIC 213 can directly remotely operate the address of the SQ1 in the SSD 244”), wherein the at least one SSQ is released responsive to a number of the plurality of QPs reaching a first threshold (see paragraphs 0094 and 0110), and the pool of SSQs is pinned in the memory (see fig. 2) such that the pinned pool of SSQs is not paged out to a disk (note, this is a negative limitation that takes place when the system is off).
3. As per claim 9, He discloses wherein a send queue (SQ) of one of the first QP or the second QP is pinned in the user space of the memory (see fig. 2 and paragraph 0051).
4. As per claim 10, He discloses wherein a QP context of one of the first QP or the second QP is pinned in the kernel space of the memory (see paragraph 0070).
5. As per claim 11, He discloses wherein QP information is in swappable portions of one of the user space or the kernel space of the memory (see paragraphs 0058 and 0084).
6. As per claim 12, He discloses wherein the pool is set responsive to a second number of the plurality of QPs being set reaching a second threshold (see paragraphs 0058 and 0084).
7. As per claim 13, He discloses wherein the system uses a pool of incoming read request queues (IRRQs), and the at least one SSQ uses a corresponding outgoing read request queue (ORRQ) (see paragraphs 0054, 0095 and 0110).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1, 2, 4-6, 14, 15 and 17-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over He et al. (US pub. # 2023/0342087), hereinafter, “He”, in view of Tringale et al. (US pat. # 9,952,776), hereinafter, “Tringale”
10. As per claims 1, 14 and 20, He discloses a system comprising: one or more processors (CPU 341 of fig. 2, as disclose in paragraphs 0054, 0058 and 0070), coupled to memory (memory 342), the processor configured to: set in the memory a pool of shared send queues (SSQs) (plurality of SQs in memory 342; see paragraph 0054, which discloses “in addition, the SSD 244 includes a plurality of SQs and CQs, and a maximum quantity of SQs and a maximum quantity of CQs may be supported to 64,000. However, in consideration of memory and performance, a maximum quantity of 256 is typically selected currently. The application server 210 is used as an example, to describe a specific binding process of the SQ and the QP. The application server 210 registers the memory 212 required for data communication with the RNIC 213, and the storage server 240 registers the memory 242 required for data communication with the RNIC 243, so that the RNIC 213 and the RNIC 243 can operate the memory 242 and the memory 212 in an RDMA manner. In addition, the storage server 240 binds the SQs in the SSD 244 to the stored QPs one by one, for example, binds the QP1 connected to the application server 210 to an SQ1. Then, an address of the SQ1 is mapped, and a virtual address obtained through mapping is registered with the RNIC 243. The RNIC 243 sends the address of the SQ1 to the RNIC 213 through an RDMA connection, so that the RNIC 213 can directly remotely operate the address of the SQ1 in the SSD 244. During data writing, the application server 210 generates data by using the CPU 211 and stores the generated data in the memory 212, then writes the data into the memory 242 of the storage server 240 through the RNIC 213, and notifies, based on the SQ address of the SSD 244, the SSD 244 to migrate the data in the memory 242 to the SSD 244 for persistent storage. If another application server needs to write data to the storage server 240, a process is similar to that in the foregoing description, and details are not described herein again”), wherein at least one SSQ (SQ1 of memory 342 combined with SQ2 of memory 342. Note, the recited phrase ‘at least one’ is opened to one or more; in other words, the combination of SQ1 and SQ2 has at least one in it) in the pool (see paragraph 0054, which teaches multiples of SQs and associated QPs or any number of SQs, QPs) of SSQs SSQ in the pool of SSQs is configured for use as a send queue (SQ) for a plurality of queue pairs (QPs) (QP1 and QP2 in memory 342; see fig. 2 and paragraph 0054); responsive to a process in a user space (see paragraph 0045, which discloses “the host is configured to generate or consume data, for example, may be an application server, a distributed file system server, or the like” and fig. 5, which discloses data from a server, host to a SQ, QP. The data came from the server, a user space. Note, the claim language doesn’t provide much detail in regards to a ‘user space’), allocate the at least one SSQ from the pool of SSQs to the plurality of QPs (see fig. 2 and paragraph 0054), the at least one SSQ set for a process having a plurality of connections to a plurality of remote processes (see paragraph 0054, which discloses “Each application server is connected to the storage server, to form a QP. Therefore, the memory 242 of the storage server 240 has a plurality of QPs, for example, a QP1, a QP2, and a QP3, and each QP corresponds to a connection between the storage server 240 and one application server. ... The application server 210 is used as an example, to describe a specific binding process of the SQ and the QP…. In addition, the storage server 240 binds the SQs in the SSD 244 to the stored QPs one by one, for example, binds the QP1 connected to the application server 210 to an SQ1. Then, an address of the SQ1 is mapped, and a virtual address obtained through mapping is registered with the RNIC 243. The RNIC 243 sends the address of the SQ1 to the RNIC 213 through an RDMA connection, so that the RNIC 213 can directly remotely operate the address of the SQ1 in the SSD 244”); and send by the at least one SSQ, via the plurality of connections, outgoing messages to separate remote processes of the plurality of remote processes (see fig. 2 and paragraph 0054, which discloses “Each application server is connected to the storage server, to form a QP. Therefore, the memory 242 of the storage server 240 has a plurality of QPs, for example, a QP1, a QP2, and a QP3, and each QP corresponds to a connection between the storage server 240 and one application server. ... The application server 210 is used as an example, to describe a specific binding process of the SQ and the QP…. In addition, the storage server 240 binds the SQs in the SSD 244 to the stored QPs one by one, for example, binds the QP1 connected to the application server 210 to an SQ1. Then, an address of the SQ1 is mapped, and a virtual address obtained through mapping is registered with the RNIC 243. The RNIC 243 sends the address of the SQ1 to the RNIC 213 through an RDMA connection, so that the RNIC 213 can directly remotely operate the address of the SQ1 in the SSD 244”), wherein the pool of SSQs is pinned in the memory (see fig. 2).
He fails to specifically disclose the at least one SSQ is released to the pool by a QP responsive to identifying that a SQ of the QP is empty.
Tringale discloses the at least one SSQ is released to the pool by a QP responsive to identifying that a SQ of the QP is empty (see col. 6, lines 20-31, which discloses “Any of a wide variety of prioritization techniques could be used, but for purposes of illustration the medium latency QP 702 does not transmit until the corresponding low latency QP 700 transmit queue 706 is empty, and the high latency QP 704 does not transmit until the corresponding medium latency QP transmit queue 708 is empty. The QPIF resource controller selects a corresponding QP from the pool based on the indicated quality of service. The selected QP is returned to the requestor and then used for executing the transaction. If a corresponding QP is not available from the pool then a “no path available” reply is returned to the client”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Tringale’s teaching of a data storage system utilizing queue pairs associated with point-to-point links to perform RDMA transactions with memory components, into He’s teaching of a network device to receive access requests sent by a plurality of clients connected to the network device using RDMA, for the benefit of reducing postings to a relatively higher priority link when a corresponding relatively lower priority link is starved of bandwidth, improving loads among multiple links.
11. As per claims 2 and 15, the combination of He and Tringale discloses “The system of claim 1” [See rejection to claim 1 above], wherein the pool is set responsive to a first number of the QPs reaching a threshold (see paragraph 0054 of He).
12. As per claims 4 and 17, He discloses wherein the at least one SSQ is used as the SQ for at least one QP instead of an individual SQ for each QP (see paragraph 0054 and above explaining claim ‘at least one’ SSQ being equated to the combination of SQ1 and SQ2 of memory 342).
13. As per claims 5 and 18, He discloses wherein the system uses a pool of incoming read request queues (IRRQs), and the at least one SSQ uses a corresponding outgoing read request queue (ORRQ) (see paragraphs 0054, 0095 and 0110).
14. As per claims 6 and 19, He discloses wherein a QP is set to have a pointer to the at least one SSQ in the pool of SSQs (see paragraph 0084).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1, 2, 4-6, 8-15 and 17-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
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